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rm commented out AddGC tests
1 parent 0b6a046 commit 070fab3

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2 files changed

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-16
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2 files changed

+0
-16
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src/neg_tests/ref_stm_dom_tests.ml

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@@ -2,17 +2,9 @@ open Ref_stm_spec
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module RT_int = STM_domain.Make(RConf_int)
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module RT_int64 = STM_domain.Make(RConf_int64)
5-
6-
(*module RConf_int_GC = STM_base.AddGC(RConf_int)*)
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(*module RConf_int64_GC = STM_base.AddGC(RConf_int64)*)
8-
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(*module RT_int_GC = STM_domain.Make(RConf_int_GC)*)
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(*module RT_int64_GC = STM_domain.Make(RConf_int64_GC)*)
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;;
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QCheck_runner.run_tests_main
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(let count = 1000 in
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[RT_int.neg_agree_test_par ~count ~name:"STM int ref test parallel";
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(*RT_int_GC.neg_agree_test_par ~count ~name:"STM int ref test parallel (w/AddGC functor)";*)
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RT_int64.neg_agree_test_par ~count ~name:"STM int64 ref test parallel";
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(*RT_int64_GC.neg_agree_test_par ~count ~name:"STM int64 ref test parallel (w/AddGC functor)";*)
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])

src/neg_tests/ref_stm_thread_tests.ml

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2,17 +2,9 @@ open Ref_stm_spec
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module RT_int = STM_thread.Make(RConf_int)
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module RT_int64 = STM_thread.Make(RConf_int64)
5-
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(*module RConf_int_GC = STM_base.AddGC(RConf_int)*)
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(*module RConf_int64_GC = STM_base.AddGC(RConf_int64)*)
8-
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(*module RT_int_GC = STM_thread.Make(RConf_int_GC)*)
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(*module RT_int64_GC = STM_thread.Make(RConf_int64_GC)*)
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;;
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QCheck_runner.run_tests_main
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(let count = 1000 in
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[RT_int.agree_test_conc ~count ~name:"STM int ref test with Thread";
15-
(*RT_int_GC.agree_test_conc ~count ~name:"STM int ref test with Thread (w/AddGC functor)";*)
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RT_int64.neg_agree_test_conc ~count ~name:"STM int64 ref test with Thread";
17-
(*RT_int64_GC.agree_test_conc ~count ~name:"STM int64 ref test with Thread (w/AddGC functor)";*)
1810
])

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