Add genben GA_94 demo: 5-stage pipelined RISC-V CPU through placement

GenBen is a benchmark suite for LLM-generated hardware designs. GA_94
is a 5-stage pipelined RISC-V CPU (22 modules, 14K cells on ASAP7).

Patches fix upstream _ref suffixes and trailing commas in port lists
via patch_cmds in MODULE.bazel.

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

Author: oharboe

MODULE.bazel

@@ -260,6 +260,20 @@ http_archive(
     urls = ["https://github.com/profitmonk/tensor_accelerator/archive/ae1078d296a995925c81f5ae643a4574d5971589.tar.gz"],
 )
 
+http_archive(
+    name = "genben",
+    build_file = "//genben:external.BUILD.bazel",
+    patch_cmds = [
+        # Remove _ref suffix from all module names so the top module is just "CPU"
+        "sed -i 's/_ref\\b//g' data/Design/GA_94/ref.v",
+        # Fix trailing commas before ); in port lists (illegal in strict Verilog)
+        "sed -i -E ':a;N;$!ba;s/,([[:space:]]*\\);)/\\1/g' data/Design/GA_94/ref.v",
+    ],
+    sha256 = "22a27982fc10d9fba27828a955a551d017bf0195bede283a0f9ae58de50cead8",
+    strip_prefix = "GenBen-a103f9a892e31bd1c410fe23663bc89f029c6fe9",
+    urls = ["https://github.com/ChatDesignVerification/GenBen/archive/a103f9a892e31bd1c410fe23663bc89f029c6fe9.tar.gz"],
+)
+
 http_archive(
     name = "pymtl3",
     build_file = "//pymtl3:external.BUILD.bazel",

README.md

@@ -70,6 +70,7 @@ results. See [PHILOSOPHY.md](PHILOSOPHY.md) for the approach.
 | [pymtl3](pymtl3/) | Stream checksum unit (pymtl3) | ASAP7 | — | 0.42 GHz | 1,678 | 192 | `46ea257` | `ea5ca68` | 2026-03-24 | Done |
 | [cva6](cva6/) | RISC-V CPU (CVA6 cv32a60x, HPDcache) | ASAP7 | — | 0.29 GHz | 80,306 | 15,189 | | `02e11e3` | 2026-03-25 | Place |
 | [tensor_accelerator](tensor_accelerator/) | 4-level hierarchical TPU (4×TPC, systolic arrays) | ASAP7 | — | — | — | 44,562 | | `ae1078d` | 2026-03-25 | CTS |
+| [genben](genben/) | 5-stage pipelined RISC-V CPU (GenBen GA_94) | ASAP7 | — | — | 14,032 | — | | `a103f9a` | 2026-03-25 | Place |
 
 <details>
 <summary>Column descriptions</summary>
@@ -99,9 +100,9 @@ _Run `/demo-update <project>` to refresh statistics after a build._
 |:--------:|:--------:|:--------:|:--------:|:--------:|
 | [<img src="docs/gemmini_8x8/route.webp" width="150">](gemmini_8x8/) | [<img src="docs/gemmini_8x8_abutted/route.webp" width="150">](gemmini_8x8_abutted/) | [<img src="docs/gemmini/route.webp" width="150">](gemmini/) | [<img src="docs/coralnpu/route.webp" width="150">](coralnpu/) | [<img src="docs/pymtl3/route.webp" width="150">](pymtl3/) |
 
-| [cva6](cva6/) | [tensor_accelerator](tensor_accelerator/) |
-|:--------:|:--------:|
-| [<img src="docs/cva6/route.webp" width="150">](cva6/) | [<img src="docs/tensor_accelerator/place.webp" width="150">](tensor_accelerator/) |
+| [cva6](cva6/) | [tensor_accelerator](tensor_accelerator/) | [genben](genben/) |
+|:--------:|:--------:|:--------:|
+| [<img src="docs/cva6/route.webp" width="150">](cva6/) | [<img src="docs/tensor_accelerator/place.webp" width="150">](tensor_accelerator/) | [<img src="docs/genben/place.webp" width="150">](genben/) |
 
 ## Upcoming
 

docs/genben/place.webp

@@ -0,0 +1,37 @@
+load("//:defs.bzl", "demo_flow", "demo_gallery_image", "demo_stage_images")
+
+demo_flow(
+    name = "CPU",
+    verilog_files = ["@genben//:rtl"],
+    arguments = {
+        # --- Synthesis ---
+        "SYNTH_HIERARCHICAL": "1",
+        "SYNTH_MINIMUM_KEEP_SIZE": "0",
+        # --- Floorplan & Placement ---
+        "CORE_UTILIZATION": "40",
+        "PLACE_DENSITY": "0.65",
+        # --- Speed defaults (remove to improve QoR) ---
+        "GPL_ROUTABILITY_DRIVEN": "0",
+        "GPL_TIMING_DRIVEN": "0",
+        "SKIP_CTS_REPAIR_TIMING": "1",
+        "SKIP_INCREMENTAL_REPAIR": "1",
+        "SKIP_LAST_GASP": "1",
+        "FILL_CELLS": "",
+        "TAPCELL_TCL": "",
+    },
+    sources = {
+        "SDC_FILE": [":constraints.sdc"],
+    },
+    substeps = True,
+)
+
+demo_gallery_image(
+    name = "CPU_gallery",
+    src = ":CPU_place",
+)
+
+demo_stage_images(
+    name = "CPU_images",
+    module = "CPU",
+    stages = ["floorplan", "place", "cts", "route"],
+)

genben/BUILD.bazel

@@ -0,0 +1,6 @@
+# 1000ps = 1 GHz — aggressive target for ASAP7
+set clk_name  clk_i
+set clk_port_name clk_i
+set clk_period 1000
+
+source $::env(PLATFORM_DIR)/constraints.sdc

genben/constraints.sdc

@@ -0,0 +1,5 @@
+filegroup(
+    name = "rtl",
+    srcs = ["data/Design/GA_94/ref.v"],
+    visibility = ["//visibility:public"],
+)