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The sample used to have a default size of 256x256 for both Stratix10 and Agilex devices.
This large size made the compiles very long for little benefit.
In addition, not all Agilex devices will fit such large QRDs.
Copy file name to clipboardExpand all lines: DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/README.md
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| Device | Throughput
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|:--- |:---
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| Terasic’s DE10-Agilex Development Board| 15k matrices/s for complex matrices of size 256 * 256
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| Intel® FPGA SmartNIC N6001-PL | 50k matrices/s for complex matrices of size 128 * 128
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## Key Implementation Details
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## Example Output
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Example output when running on **Terasic’s DE10-Agilex Development Board** for the decomposition of 8 matrices 819200 times (each matrix consisting of 256x256 complex numbers).
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Example output when running on **Intel® FPGA SmartNIC N6001-PL** for the decomposition of 8 matrices 819200 times (each matrix consisting of 256x256 complex numbers).
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```
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Running on device: de10_agilex : Agilex Reference Platform (aclde10_agilex0)
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Generating 8 random complex matrices of size 256x256
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Running on device: ofs_n6001 : Intel OFS Platform (ofs_ee00000)
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Generating 8 random complex matrices of size 128x128
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Running QR decomposition of 8 matrices 819200 times
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