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Copy file name to clipboardExpand all lines: DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/svd/README.md
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> **Note**: Refer to the [Performance Disclaimers](/DirectProgramming/C++SYCL_FPGA/README.md#performance-disclaimers) section for important performance information.
|Intel® FPGA SmartNIC N6001-PL| 128 x 16 | 1531 matrices/s|
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## Key Implementation Details
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This SVD design consists of 4 computation kernels, as well as several memory access kernels to handle input and output. These kernels are connected through inter-kernel pipes and input/output through unified shared memory (USM).
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## Example Output
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Example Output when running on the **Silicom FPGA SmartNIC N6011**.
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Example Output when running on the **Intel® FPGA SmartNIC N6001-PL**.
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```
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Running on device: ofs_n6001 : Intel OFS Platform (ofs_ee00000)
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Code samples are licensed under the MIT license. See [License.txt](/License.txt) for details.
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Third party program Licenses can be found here: [third-party-programs.txt](/third-party-programs.txt).
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Third party program Licenses can be found here: [third-party-programs.txt](/third-party-programs.txt).
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