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These two properties allow the program to specify a maximum work-group
size in various ways.
They are intended to be targeted from languages such as SYCL (see
intel/llvm#14518).
This PR implements them for CUDA and Native CPU. It should also be able
support them for HIP, in the same fashion. Other adapters using SPIR-V
and/or Level Zero would require further changes to both of those
specifications.
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