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[CTS] Add new urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations test for checking different combinations of allocation size/alignment.
1 parent b915354 commit dfcda7b

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5 files changed

+135
-9
lines changed

5 files changed

+135
-9
lines changed

‎test/conformance/enqueue/helpers.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -73,8 +73,8 @@ print2DTestString(const testing::TestParamInfo<typename T::ParamType> &info) {
7373
const auto platform_device_name =
7474
uur::GetPlatformAndDeviceName(device_handle);
7575
std::stringstream test_name;
76-
auto src_kind = std::get<1>(std::get<1>(info.param));
77-
auto dst_kind = std::get<2>(std::get<1>(info.param));
76+
const auto src_kind = std::get<1>(std::get<1>(info.param));
77+
const auto dst_kind = std::get<2>(std::get<1>(info.param));
7878
test_name << platform_device_name << "__pitch__"
7979
<< std::get<0>(std::get<1>(info.param)).pitch << "__width__"
8080
<< std::get<0>(std::get<1>(info.param)).width << "__height__"

‎test/conformance/usm/urUSMDeviceAlloc.cpp

Lines changed: 73 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2,21 +2,47 @@
22
// Part of the Unified-Runtime Project, under the Apache License v2.0 with LLVM Exceptions.
33
// See LICENSE.TXT
44
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
5-
65
#include <uur/fixtures.h>
76

8-
struct urUSMDeviceAllocTest : uur::urQueueTestWithParam<uur::BoolTestParam> {
7+
using USMDeviceAllocParams = std::tuple<uur::BoolTestParam, uint32_t, size_t>;
8+
9+
template <typename T>
10+
inline std::string printUSMDeviceAllocTestString(
11+
const testing::TestParamInfo<typename T::ParamType> &info) {
12+
// ParamType will be std::tuple<ur_device_handle_t, USMDeviceAllocParams>
13+
const auto device_handle = std::get<0>(info.param);
14+
const auto platform_device_name =
15+
uur::GetPlatformAndDeviceName(device_handle);
16+
const auto usmDeviceAllocParams = std::get<1>(info.param);
17+
const auto BoolParam = std::get<0>(usmDeviceAllocParams);
18+
19+
std::stringstream ss;
20+
ss << BoolParam.name << (BoolParam.value ? "Enabled" : "Disabled");
21+
22+
const auto alignment = std::get<1>(usmDeviceAllocParams);
23+
const auto size = std::get<2>(usmDeviceAllocParams);
24+
if (alignment && size > 0) {
25+
ss << "_";
26+
ss << std::get<1>(usmDeviceAllocParams);
27+
ss << "_";
28+
ss << std::get<2>(usmDeviceAllocParams);
29+
}
30+
31+
return platform_device_name + "__" + ss.str();
32+
}
33+
34+
struct urUSMDeviceAllocTest : uur::urQueueTestWithParam<USMDeviceAllocParams> {
935
void SetUp() override {
1036
UUR_RETURN_ON_FATAL_FAILURE(
11-
uur::urQueueTestWithParam<uur::BoolTestParam>::SetUp());
37+
uur::urQueueTestWithParam<USMDeviceAllocParams>::SetUp());
1238
ur_device_usm_access_capability_flags_t deviceUSMSupport = 0;
1339
ASSERT_SUCCESS(
1440
uur::GetDeviceUSMDeviceSupport(device, deviceUSMSupport));
1541
if (!deviceUSMSupport) {
1642
GTEST_SKIP() << "Device USM is not supported.";
1743
}
1844

19-
if (getParam().value) {
45+
if (usePool) {
2046
ur_usm_pool_desc_t pool_desc = {};
2147
ASSERT_SUCCESS(urUSMPoolCreate(context, &pool_desc, &pool));
2248
}
@@ -27,16 +53,20 @@ struct urUSMDeviceAllocTest : uur::urQueueTestWithParam<uur::BoolTestParam> {
2753
ASSERT_SUCCESS(urUSMPoolRelease(pool));
2854
}
2955
UUR_RETURN_ON_FATAL_FAILURE(
30-
uur::urQueueTestWithParam<uur::BoolTestParam>::TearDown());
56+
uur::urQueueTestWithParam<USMDeviceAllocParams>::TearDown());
3157
}
3258

3359
ur_usm_pool_handle_t pool = nullptr;
60+
bool usePool = std::get<0>(getParam()).value;
3461
};
3562

63+
// The 0 value parameters are not relevant for urUSMDeviceAllocTest tests, they are used below in urUSMDeviceAllocAlignmentTest
3664
UUR_TEST_SUITE_P(
3765
urUSMDeviceAllocTest,
38-
testing::ValuesIn(uur::BoolTestParam::makeBoolParam("UsePool")),
39-
uur::deviceTestWithParamPrinter<uur::BoolTestParam>);
66+
testing::Combine(
67+
testing::ValuesIn(uur::BoolTestParam::makeBoolParam("UsePool")),
68+
testing::Values(0), testing::Values(0)),
69+
printUSMDeviceAllocTestString<urUSMDeviceAllocTest>);
4070

4171
TEST_P(urUSMDeviceAllocTest, Success) {
4272
void *ptr = nullptr;
@@ -69,6 +99,7 @@ TEST_P(urUSMDeviceAllocTest, SuccessWithDescriptors) {
6999
size_t allocation_size = sizeof(int);
70100
ASSERT_SUCCESS(urUSMDeviceAlloc(context, device, &usm_desc, pool,
71101
allocation_size, &ptr));
102+
ASSERT_NE(ptr, nullptr);
72103

73104
ur_event_handle_t event = nullptr;
74105
uint8_t pattern = 0;
@@ -116,3 +147,38 @@ TEST_P(urUSMDeviceAllocTest, InvalidValueAlignPowerOfTwo) {
116147
UR_RESULT_ERROR_INVALID_VALUE,
117148
urUSMDeviceAlloc(context, device, &desc, pool, sizeof(int), &ptr));
118149
}
150+
151+
using urUSMDeviceAllocAlignmentTest = urUSMDeviceAllocTest;
152+
153+
UUR_TEST_SUITE_P(
154+
urUSMDeviceAllocAlignmentTest,
155+
testing::Combine(
156+
testing::ValuesIn(uur::BoolTestParam::makeBoolParam("UsePool")),
157+
testing::Values(4, 8, 16, 32, 64), testing::Values(8, 512, 2048)),
158+
printUSMDeviceAllocTestString<urUSMDeviceAllocAlignmentTest>);
159+
160+
TEST_P(urUSMDeviceAllocAlignmentTest, SuccessAlignedAllocations) {
161+
uint32_t alignment = std::get<1>(getParam());
162+
size_t allocation_size = std::get<2>(getParam());
163+
164+
ur_usm_device_desc_t usm_device_desc{UR_STRUCTURE_TYPE_USM_DEVICE_DESC,
165+
nullptr,
166+
/* device flags */ 0};
167+
168+
ur_usm_desc_t usm_desc{UR_STRUCTURE_TYPE_USM_DESC, &usm_device_desc,
169+
/* mem advice flags */ UR_USM_ADVICE_FLAG_DEFAULT,
170+
alignment};
171+
void *ptr = nullptr;
172+
ASSERT_SUCCESS(urUSMDeviceAlloc(context, device, &usm_desc, pool,
173+
allocation_size, &ptr));
174+
ASSERT_NE(ptr, nullptr);
175+
176+
ur_event_handle_t event = nullptr;
177+
uint8_t pattern = 0;
178+
ASSERT_SUCCESS(urEnqueueUSMFill(queue, ptr, sizeof(pattern), &pattern,
179+
allocation_size, 0, nullptr, &event));
180+
ASSERT_SUCCESS(urEventWait(1, &event));
181+
182+
ASSERT_SUCCESS(urUSMFree(context, ptr));
183+
EXPECT_SUCCESS(urEventRelease(event));
184+
}

‎test/conformance/usm/usm_adapter_hip.match

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,21 @@
66
{{OPT}}urUSMDeviceAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
77
{{OPT}}urUSMDeviceAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolDisabled
88
{{OPT}}urUSMDeviceAllocTest.InvalidValueAlignPowerOfTwo/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
9+
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_8
10+
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_512
11+
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_2048
12+
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_8
13+
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_512
14+
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_2048
15+
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_8
16+
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_512
17+
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_2048
18+
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_8
19+
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_512
20+
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_2048
21+
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_8
22+
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_512
23+
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_2048
924
{{OPT}}urUSMGetMemAllocInfoTest.Success/AMD_HIP_BACKEND___{{.*}}___UR_USM_ALLOC_INFO_BASE_PTR
1025
{{OPT}}urUSMGetMemAllocInfoTest.Success/AMD_HIP_BACKEND___{{.*}}___UR_USM_ALLOC_INFO_SIZE
1126
{{OPT}}urUSMGetMemAllocInfoTest.Success/AMD_HIP_BACKEND___{{.*}}___UR_USM_ALLOC_INFO_POOL

‎test/conformance/usm/usm_adapter_native_cpu.match

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,36 @@ urUSMDeviceAllocTest.InvalidUSMSize/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolE
1212
urUSMDeviceAllocTest.InvalidUSMSize/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled
1313
urUSMDeviceAllocTest.InvalidValueAlignPowerOfTwo/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled
1414
urUSMDeviceAllocTest.InvalidValueAlignPowerOfTwo/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled
15+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_4_8
16+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_4_512
17+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_4_2048
18+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_8_8
19+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_8_512
20+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_8_2048
21+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_16_8
22+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_16_512
23+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_16_2048
24+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_32_8
25+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_32_512
26+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_32_2048
27+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_64_8
28+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_64_512
29+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_64_2048
30+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_4_8
31+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_4_512
32+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_4_2048
33+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_8_8
34+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_8_512
35+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_8_2048
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urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_16_8
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urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_16_512
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urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_16_2048
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urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_32_8
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urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_32_512
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urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_32_2048
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urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_64_8
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urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_64_512
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urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_64_2048
1545
urUSMFreeTest.SuccessDeviceAlloc/SYCL_NATIVE_CPU___SYCL_Native_CPU_
1646
urUSMFreeTest.SuccessHostAlloc/SYCL_NATIVE_CPU___SYCL_Native_CPU_
1747
urUSMFreeTest.SuccessSharedAlloc/SYCL_NATIVE_CPU___SYCL_Native_CPU_

‎test/conformance/usm/usm_adapter_opencl.match

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,21 @@ urUSMDeviceAllocTest.InvalidNullHandleDevice/Intel_R__OpenCL___{{.*}}___UsePoolE
55
urUSMDeviceAllocTest.InvalidNullPtrResult/Intel_R__OpenCL___{{.*}}___UsePoolEnabled
66
urUSMDeviceAllocTest.InvalidUSMSize/Intel_R__OpenCL___{{.*}}___UsePoolEnabled
77
urUSMDeviceAllocTest.InvalidValueAlignPowerOfTwo/Intel_R__OpenCL___{{.*}}___UsePoolEnabled
8+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_4_8
9+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_4_512
10+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_4_2048
11+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_8_8
12+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_8_512
13+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_8_2048
14+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_16_8
15+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_16_512
16+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_16_2048
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urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_32_8
18+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_32_512
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urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_32_2048
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urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_64_8
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urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_64_512
22+
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_64_2048
823
urUSMGetMemAllocInfoTest.Success/Intel_R__OpenCL___{{.*}}___UR_USM_ALLOC_INFO_POOL
924
urUSMHostAllocTest.Success/Intel_R__OpenCL___{{.*}}___UsePoolEnabled
1025
urUSMHostAllocTest.SuccessWithDescriptors/Intel_R__OpenCL___{{.*}}___UsePoolEnabled

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