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[llvm][ScheduleDAG] Re-arrange SUnit's members to make it smaller (llvm#94547)
before: ``` *** Dumping AST Record Layout 0 | class llvm::SUnit 0 | SDNode * Node 8 | MachineInstr * Instr 16 | SUnit * OrigNode 24 | const MCSchedClassDesc * SchedClass 32 | class llvm::SmallVector<class llvm::SDep, 4> Preds 32 | class llvm::SmallVectorImpl<class llvm::SDep> (base) 32 | class llvm::SmallVectorTemplateBase<class llvm::SDep> (base) 32 | class llvm::SmallVectorTemplateCommon<class llvm::SDep> (base) 32 | class llvm::SmallVectorBase<uint32_t> (base) 32 | void * BeginX 40 | unsigned int Size 44 | unsigned int Capacity 48 | struct llvm::SmallVectorStorage<class llvm::SDep, 4> (base) 48 | char[64] InlineElts 112 | class llvm::SmallVector<class llvm::SDep, 4> Succs 112 | class llvm::SmallVectorImpl<class llvm::SDep> (base) 112 | class llvm::SmallVectorTemplateBase<class llvm::SDep> (base) 112 | class llvm::SmallVectorTemplateCommon<class llvm::SDep> (base) 112 | class llvm::SmallVectorBase<uint32_t> (base) 112 | void * BeginX 120 | unsigned int Size 124 | unsigned int Capacity 128 | struct llvm::SmallVectorStorage<class llvm::SDep, 4> (base) 128 | char[64] InlineElts 192 | unsigned int NodeNum 196 | unsigned int NodeQueueId 200 | unsigned int NumPreds 204 | unsigned int NumSuccs 208 | unsigned int NumPredsLeft 212 | unsigned int NumSuccsLeft 216 | unsigned int WeakPredsLeft 220 | unsigned int WeakSuccsLeft 224 | unsigned short NumRegDefsLeft 226 | unsigned short Latency 228:0-0 | _Bool isVRegCycle 228:1-1 | _Bool isCall 228:2-2 | _Bool isCallOp 228:3-3 | _Bool isTwoAddress 228:4-4 | _Bool isCommutable 228:5-5 | _Bool hasPhysRegUses 228:6-6 | _Bool hasPhysRegDefs 228:7-7 | _Bool hasPhysRegClobbers 229:0-0 | _Bool isPending 229:1-1 | _Bool isAvailable 229:2-2 | _Bool isScheduled 229:3-3 | _Bool isScheduleHigh 229:4-4 | _Bool isScheduleLow 229:5-5 | _Bool isCloned 229:6-6 | _Bool isUnbuffered 229:7-7 | _Bool hasReservedResource 232 | Sched::Preference SchedulingPref 236:0-0 | _Bool isDepthCurrent 236:1-1 | _Bool isHeightCurrent 240 | unsigned int Depth 244 | unsigned int Height 248 | unsigned int TopReadyCycle 252 | unsigned int BotReadyCycle 256 | const TargetRegisterClass * CopyDstRC 264 | const TargetRegisterClass * CopySrcRC | [sizeof=272, dsize=272, align=8, | nvsize=272, nvalign=8] ``` after: ``` *** Dumping AST Record Layout 0 | class llvm::SUnit 0 | union llvm::SUnit::(anonymous at /Users/jonathan_roelofs/llvm-upstream/llvm/include/llvm/CodeGen/ScheduleDAG.h:246:5) 0 | SDNode * Node 0 | MachineInstr * Instr 8 | SUnit * OrigNode 16 | const MCSchedClassDesc * SchedClass 24 | const TargetRegisterClass * CopyDstRC 32 | const TargetRegisterClass * CopySrcRC 40 | class llvm::SmallVector<class llvm::SDep, 4> Preds 40 | class llvm::SmallVectorImpl<class llvm::SDep> (base) 40 | class llvm::SmallVectorTemplateBase<class llvm::SDep> (base) 40 | class llvm::SmallVectorTemplateCommon<class llvm::SDep> (base) 40 | class llvm::SmallVectorBase<uint32_t> (base) 40 | void * BeginX 48 | unsigned int Size 52 | unsigned int Capacity 56 | struct llvm::SmallVectorStorage<class llvm::SDep, 4> (base) 56 | char[64] InlineElts 120 | class llvm::SmallVector<class llvm::SDep, 4> Succs 120 | class llvm::SmallVectorImpl<class llvm::SDep> (base) 120 | class llvm::SmallVectorTemplateBase<class llvm::SDep> (base) 120 | class llvm::SmallVectorTemplateCommon<class llvm::SDep> (base) 120 | class llvm::SmallVectorBase<uint32_t> (base) 120 | void * BeginX 128 | unsigned int Size 132 | unsigned int Capacity 136 | struct llvm::SmallVectorStorage<class llvm::SDep, 4> (base) 136 | char[64] InlineElts 200 | unsigned int NodeNum 204 | unsigned int NodeQueueId 208 | unsigned int NumPreds 212 | unsigned int NumSuccs 216 | unsigned int NumPredsLeft 220 | unsigned int NumSuccsLeft 224 | unsigned int WeakPredsLeft 228 | unsigned int WeakSuccsLeft 232 | unsigned int TopReadyCycle 236 | unsigned int BotReadyCycle 240 | unsigned int Depth 244 | unsigned int Height 248:0-0 | _Bool isVRegCycle 248:1-1 | _Bool isCall 248:2-2 | _Bool isCallOp 248:3-3 | _Bool isTwoAddress 248:4-4 | _Bool isCommutable 248:5-5 | _Bool hasPhysRegUses 248:6-6 | _Bool hasPhysRegDefs 248:7-7 | _Bool hasPhysRegClobbers 249:0-0 | _Bool isPending 249:1-1 | _Bool isAvailable 249:2-2 | _Bool isScheduled 249:3-3 | _Bool isScheduleHigh 249:4-4 | _Bool isScheduleLow 249:5-5 | _Bool isCloned 249:6-6 | _Bool isUnbuffered 249:7-7 | _Bool hasReservedResource 250 | unsigned short NumRegDefsLeft 252 | unsigned short Latency 254:0-0 | _Bool isDepthCurrent 254:1-1 | _Bool isHeightCurrent 254:2-2 | _Bool isNode 254:3-3 | _Bool isInst 254:4-7 | Sched::Preference SchedulingPref | [sizeof=256, dsize=255, align=8, | nvsize=255, nvalign=8] ```
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‎llvm/include/llvm/CodeGen/ScheduleDAG.h‎

Lines changed: 56 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -243,8 +243,10 @@ class TargetRegisterInfo;
243243
private:
244244
enum : unsigned { BoundaryID = ~0u };
245245

246-
SDNode *Node = nullptr; ///< Representative node.
247-
MachineInstr *Instr = nullptr; ///< Alternatively, a MachineInstr.
246+
union {
247+
SDNode *Node; ///< Representative node.
248+
MachineInstr *Instr; ///< Alternatively, a MachineInstr.
249+
};
248250

249251
public:
250252
SUnit *OrigNode = nullptr; ///< If not this, the node from which this node
@@ -253,6 +255,10 @@ class TargetRegisterInfo;
253255
const MCSchedClassDesc *SchedClass =
254256
nullptr; ///< nullptr or resolved SchedClass.
255257

258+
const TargetRegisterClass *CopyDstRC =
259+
nullptr; ///< Is a special copy node if != nullptr.
260+
const TargetRegisterClass *CopySrcRC = nullptr;
261+
256262
SmallVector<SDep, 4> Preds; ///< All sunit predecessors.
257263
SmallVector<SDep, 4> Succs; ///< All sunit successors.
258264

@@ -269,8 +275,14 @@ class TargetRegisterInfo;
269275
unsigned NumSuccsLeft = 0; ///< # of succs not scheduled.
270276
unsigned WeakPredsLeft = 0; ///< # of weak preds not scheduled.
271277
unsigned WeakSuccsLeft = 0; ///< # of weak succs not scheduled.
272-
unsigned short NumRegDefsLeft = 0; ///< # of reg defs with no scheduled use.
273-
unsigned short Latency = 0; ///< Node latency.
278+
unsigned TopReadyCycle = 0; ///< Cycle relative to start when node is ready.
279+
unsigned BotReadyCycle = 0; ///< Cycle relative to end when node is ready.
280+
281+
private:
282+
unsigned Depth = 0; ///< Node depth.
283+
unsigned Height = 0; ///< Node height.
284+
285+
public:
274286
bool isVRegCycle : 1; ///< May use and def the same vreg.
275287
bool isCall : 1; ///< Is a function call.
276288
bool isCallOp : 1; ///< Is a function call operand.
@@ -287,52 +299,54 @@ class TargetRegisterInfo;
287299
bool isCloned : 1; ///< True if this node has been cloned.
288300
bool isUnbuffered : 1; ///< Uses an unbuffered resource.
289301
bool hasReservedResource : 1; ///< Uses a reserved resource.
290-
Sched::Preference SchedulingPref = Sched::None; ///< Scheduling preference.
302+
unsigned short NumRegDefsLeft = 0; ///< # of reg defs with no scheduled use.
303+
unsigned short Latency = 0; ///< Node latency.
291304

292305
private:
293306
bool isDepthCurrent : 1; ///< True if Depth is current.
294307
bool isHeightCurrent : 1; ///< True if Height is current.
295-
unsigned Depth = 0; ///< Node depth.
296-
unsigned Height = 0; ///< Node height.
308+
bool isNode : 1; ///< True if the representative is an SDNode
309+
bool isInst : 1; ///< True if the representative is a MachineInstr
297310

298311
public:
299-
unsigned TopReadyCycle = 0; ///< Cycle relative to start when node is ready.
300-
unsigned BotReadyCycle = 0; ///< Cycle relative to end when node is ready.
301-
302-
const TargetRegisterClass *CopyDstRC =
303-
nullptr; ///< Is a special copy node if != nullptr.
304-
const TargetRegisterClass *CopySrcRC = nullptr;
312+
Sched::Preference SchedulingPref : 4; ///< Scheduling preference.
313+
static_assert(Sched::Preference::Last <= (1 << 4),
314+
"not enough bits in bitfield");
305315

306316
/// Constructs an SUnit for pre-regalloc scheduling to represent an
307317
/// SDNode and any nodes flagged to it.
308318
SUnit(SDNode *node, unsigned nodenum)
309-
: Node(node), NodeNum(nodenum), isVRegCycle(false), isCall(false),
310-
isCallOp(false), isTwoAddress(false), isCommutable(false),
311-
hasPhysRegUses(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
312-
isPending(false), isAvailable(false), isScheduled(false),
313-
isScheduleHigh(false), isScheduleLow(false), isCloned(false),
314-
isUnbuffered(false), hasReservedResource(false), isDepthCurrent(false),
315-
isHeightCurrent(false) {}
319+
: Node(node), NodeNum(nodenum), isVRegCycle(false), isCall(false),
320+
isCallOp(false), isTwoAddress(false), isCommutable(false),
321+
hasPhysRegUses(false), hasPhysRegDefs(false),
322+
hasPhysRegClobbers(false), isPending(false), isAvailable(false),
323+
isScheduled(false), isScheduleHigh(false), isScheduleLow(false),
324+
isCloned(false), isUnbuffered(false), hasReservedResource(false),
325+
isDepthCurrent(false), isHeightCurrent(false), isNode(true),
326+
isInst(false), SchedulingPref(Sched::None) {}
316327

317328
/// Constructs an SUnit for post-regalloc scheduling to represent a
318329
/// MachineInstr.
319330
SUnit(MachineInstr *instr, unsigned nodenum)
320-
: Instr(instr), NodeNum(nodenum), isVRegCycle(false), isCall(false),
321-
isCallOp(false), isTwoAddress(false), isCommutable(false),
322-
hasPhysRegUses(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
323-
isPending(false), isAvailable(false), isScheduled(false),
324-
isScheduleHigh(false), isScheduleLow(false), isCloned(false),
325-
isUnbuffered(false), hasReservedResource(false), isDepthCurrent(false),
326-
isHeightCurrent(false) {}
331+
: Instr(instr), NodeNum(nodenum), isVRegCycle(false), isCall(false),
332+
isCallOp(false), isTwoAddress(false), isCommutable(false),
333+
hasPhysRegUses(false), hasPhysRegDefs(false),
334+
hasPhysRegClobbers(false), isPending(false), isAvailable(false),
335+
isScheduled(false), isScheduleHigh(false), isScheduleLow(false),
336+
isCloned(false), isUnbuffered(false), hasReservedResource(false),
337+
isDepthCurrent(false), isHeightCurrent(false), isNode(false),
338+
isInst(true), SchedulingPref(Sched::None) {}
327339

328340
/// Constructs a placeholder SUnit.
329341
SUnit()
330-
: isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(false),
331-
isCommutable(false), hasPhysRegUses(false), hasPhysRegDefs(false),
332-
hasPhysRegClobbers(false), isPending(false), isAvailable(false),
333-
isScheduled(false), isScheduleHigh(false), isScheduleLow(false),
334-
isCloned(false), isUnbuffered(false), hasReservedResource(false),
335-
isDepthCurrent(false), isHeightCurrent(false) {}
342+
: Node(nullptr), isVRegCycle(false), isCall(false), isCallOp(false),
343+
isTwoAddress(false), isCommutable(false), hasPhysRegUses(false),
344+
hasPhysRegDefs(false), hasPhysRegClobbers(false), isPending(false),
345+
isAvailable(false), isScheduled(false), isScheduleHigh(false),
346+
isScheduleLow(false), isCloned(false), isUnbuffered(false),
347+
hasReservedResource(false), isDepthCurrent(false),
348+
isHeightCurrent(false), isNode(false), isInst(false),
349+
SchedulingPref(Sched::None) {}
336350

337351
/// Boundary nodes are placeholders for the boundary of the
338352
/// scheduling region.
@@ -346,32 +360,36 @@ class TargetRegisterInfo;
346360
/// Assigns the representative SDNode for this SUnit. This may be used
347361
/// during pre-regalloc scheduling.
348362
void setNode(SDNode *N) {
349-
assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
363+
assert(!isInst && "Setting SDNode of SUnit with MachineInstr!");
350364
Node = N;
365+
isNode = true;
351366
}
352367

353368
/// Returns the representative SDNode for this SUnit. This may be used
354369
/// during pre-regalloc scheduling.
355370
SDNode *getNode() const {
356-
assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
371+
assert(!isInst && (isNode || !Instr) &&
372+
"Reading SDNode of SUnit without SDNode!");
357373
return Node;
358374
}
359375

360376
/// Returns true if this SUnit refers to a machine instruction as
361377
/// opposed to an SDNode.
362-
bool isInstr() const { return Instr; }
378+
bool isInstr() const { return isInst && Instr; }
363379

364380
/// Assigns the instruction for the SUnit. This may be used during
365381
/// post-regalloc scheduling.
366382
void setInstr(MachineInstr *MI) {
367-
assert(!Node && "Setting MachineInstr of SUnit with SDNode!");
383+
assert(!isNode && "Setting MachineInstr of SUnit with SDNode!");
368384
Instr = MI;
385+
isInst = true;
369386
}
370387

371388
/// Returns the representative MachineInstr for this SUnit. This may be used
372389
/// during post-regalloc scheduling.
373390
MachineInstr *getInstr() const {
374-
assert(!Node && "Reading MachineInstr of SUnit with SDNode!");
391+
assert(!isNode && (isInst || !Node) &&
392+
"Reading MachineInstr of SUnit without MachineInstr!");
375393
return Instr;
376394
}
377395

‎llvm/include/llvm/CodeGen/TargetLowering.h‎

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -97,14 +97,15 @@ class Value;
9797
namespace Sched {
9898

9999
enum Preference : uint8_t {
100-
None, // No preference
101-
Source, // Follow source order.
102-
RegPressure, // Scheduling for lowest register pressure.
103-
Hybrid, // Scheduling for both latency and register pressure.
104-
ILP, // Scheduling for ILP in low register pressure mode.
105-
VLIW, // Scheduling for VLIW targets.
106-
Fast, // Fast suboptimal list scheduling
107-
Linearize // Linearize DAG, no scheduling
100+
None, // No preference
101+
Source, // Follow source order.
102+
RegPressure, // Scheduling for lowest register pressure.
103+
Hybrid, // Scheduling for both latency and register pressure.
104+
ILP, // Scheduling for ILP in low register pressure mode.
105+
VLIW, // Scheduling for VLIW targets.
106+
Fast, // Fast suboptimal list scheduling
107+
Linearize, // Linearize DAG, no scheduling
108+
Last = Linearize // Marker for the last Sched::Preference
108109
};
109110

110111
} // end namespace Sched

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