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[RISCV][ISel] Add codegen support for the experimental zabha extension (llvm#80192)
This patch implements the codegen support of zabha (Byte and Halfword Atomic Memory Operations) v1.0-rc1 extension. See also https://github.com/riscv/riscv-zabha/blob/v1.0-rc1/zabha.adoc. --------- Co-authored-by: Craig Topper <[email protected]>
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‎llvm/docs/RISCVUsage.rst‎

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@@ -250,7 +250,7 @@ The primary goal of experimental support is to assist in the process of ratifica
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LLVM implements assembler support for the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0-rc1>`_.
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``experimental-zabha``
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LLVM implements assembler support for the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-zabha/tree/v1.0-rc1>`__.
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LLVM implements the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-zabha/tree/v1.0-rc1>`__.
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``experimental-zacas``
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LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zacas/releases/tag/v1.0-rc1>`__.

‎llvm/docs/ReleaseNotes.rst‎

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@@ -94,7 +94,7 @@ Changes to the PowerPC Backend
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Changes to the RISC-V Backend
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-----------------------------
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97-
* Added assembler/disassembler support for the experimental Zabha (Byte and
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* Added full support for the experimental Zabha (Byte and
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Halfword Atomic Memory Operations) extension.
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* Added assembler/disassembler support for the experimenatl Zalasr
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(Load-Acquire and Store-Release) extension.

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 15 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -641,7 +641,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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642642
if (Subtarget.hasStdExtA()) {
643643
setMaxAtomicSizeInBitsSupported(Subtarget.getXLen());
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setMinCmpXchgSizeInBits(32);
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if (Subtarget.hasStdExtZabha() && Subtarget.hasStdExtZacas())
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setMinCmpXchgSizeInBits(8);
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else
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setMinCmpXchgSizeInBits(32);
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} else if (Subtarget.hasForcedAtomics()) {
646649
setMaxAtomicSizeInBitsSupported(Subtarget.getXLen());
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} else {
@@ -19731,12 +19734,16 @@ RISCVTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
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return AtomicExpansionKind::None;
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1973319736
unsigned Size = AI->getType()->getPrimitiveSizeInBits();
19734-
if (Size == 8 || Size == 16)
19735-
return AtomicExpansionKind::MaskedIntrinsic;
19737+
if (AI->getOperation() == AtomicRMWInst::Nand) {
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if (Subtarget.hasStdExtZacas() &&
19739+
(Size >= 32 || Subtarget.hasStdExtZabha()))
19740+
return AtomicExpansionKind::CmpXChg;
19741+
if (Size < 32)
19742+
return AtomicExpansionKind::MaskedIntrinsic;
19743+
}
1973619744

19737-
if (Subtarget.hasStdExtZacas() && AI->getOperation() == AtomicRMWInst::Nand &&
19738-
(Size == Subtarget.getXLen() || Size == 32))
19739-
return AtomicExpansionKind::CmpXChg;
19745+
if (Size < 32 && !Subtarget.hasStdExtZabha())
19746+
return AtomicExpansionKind::MaskedIntrinsic;
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1974119748
return AtomicExpansionKind::None;
1974219749
}
@@ -19859,7 +19866,8 @@ RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR(
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return AtomicExpansionKind::None;
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1986119868
unsigned Size = CI->getCompareOperand()->getType()->getPrimitiveSizeInBits();
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if (Size == 8 || Size == 16)
19869+
if (!(Subtarget.hasStdExtZabha() && Subtarget.hasStdExtZacas()) &&
19870+
(Size == 8 || Size == 16))
1986319871
return AtomicExpansionKind::MaskedIntrinsic;
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return AtomicExpansionKind::None;
1986519873
}

‎llvm/lib/Target/RISCV/RISCVInstrInfoZa.td‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -185,3 +185,30 @@ let Predicates = [HasStdExtZabha, HasStdExtZacas] in {
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defm AMOCAS_B : AMO_cas_aq_rl<0b00101, 0b000, "amocas.b", GPR>;
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defm AMOCAS_H : AMO_cas_aq_rl<0b00101, 0b001, "amocas.h", GPR>;
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}
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/// AMOs
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defm : AMOPat<"atomic_swap_8", "AMOSWAP_B", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_add_8", "AMOADD_B", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_and_8", "AMOAND_B", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_or_8", "AMOOR_B", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_xor_8", "AMOXOR_B", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_max_8", "AMOMAX_B", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_min_8", "AMOMIN_B", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_umax_8", "AMOMAXU_B", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_umin_8", "AMOMINU_B", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_swap_16", "AMOSWAP_H", XLenVT, [HasStdExtZabha]>;
202+
defm : AMOPat<"atomic_load_add_16", "AMOADD_H", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_and_16", "AMOAND_H", XLenVT, [HasStdExtZabha]>;
204+
defm : AMOPat<"atomic_load_or_16", "AMOOR_H", XLenVT, [HasStdExtZabha]>;
205+
defm : AMOPat<"atomic_load_xor_16", "AMOXOR_H", XLenVT, [HasStdExtZabha]>;
206+
defm : AMOPat<"atomic_load_max_16", "AMOMAX_H", XLenVT, [HasStdExtZabha]>;
207+
defm : AMOPat<"atomic_load_min_16", "AMOMIN_H", XLenVT, [HasStdExtZabha]>;
208+
defm : AMOPat<"atomic_load_umax_16", "AMOMAXU_H", XLenVT, [HasStdExtZabha]>;
209+
defm : AMOPat<"atomic_load_umin_16", "AMOMINU_H", XLenVT, [HasStdExtZabha]>;
210+
211+
/// AMOCAS
212+
213+
defm : AMOCASPat<"atomic_cmp_swap_8", "AMOCAS_B", XLenVT, [HasStdExtZabha]>;
214+
defm : AMOCASPat<"atomic_cmp_swap_16", "AMOCAS_H", XLenVT, [HasStdExtZabha]>;

‎llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll‎

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,8 @@
77
; RUN: | FileCheck -check-prefixes=NOZACAS,RV64IA %s
88
; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zacas -verify-machineinstrs < %s \
99
; RUN: | FileCheck -check-prefixes=ZACAS,RV64IA-ZACAS %s
10+
; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zacas,+experimental-zabha -verify-machineinstrs < %s \
11+
; RUN: | FileCheck -check-prefixes=ZACAS,RV64IA-ZABHA %s
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1113
; Test cmpxchg followed by a branch on the cmpxchg success value to see if the
1214
; branch is folded into the cmpxchg expansion.
@@ -209,6 +211,16 @@ define void @cmpxchg_masked_and_branch1(ptr %ptr, i8 signext %cmp, i8 signext %v
209211
; RV64IA-ZACAS-NEXT: # %bb.5: # %do_cmpxchg
210212
; RV64IA-ZACAS-NEXT: # %bb.2: # %exit
211213
; RV64IA-ZACAS-NEXT: ret
214+
;
215+
; RV64IA-ZABHA-LABEL: cmpxchg_masked_and_branch1:
216+
; RV64IA-ZABHA: # %bb.0: # %entry
217+
; RV64IA-ZABHA-NEXT: .LBB2_1: # %do_cmpxchg
218+
; RV64IA-ZABHA-NEXT: # =>This Inner Loop Header: Depth=1
219+
; RV64IA-ZABHA-NEXT: mv a3, a1
220+
; RV64IA-ZABHA-NEXT: amocas.b.aqrl a3, a2, (a0)
221+
; RV64IA-ZABHA-NEXT: bne a3, a1, .LBB2_1
222+
; RV64IA-ZABHA-NEXT: # %bb.2: # %exit
223+
; RV64IA-ZABHA-NEXT: ret
212224
entry:
213225
br label %do_cmpxchg
214226
do_cmpxchg:
@@ -351,6 +363,16 @@ define void @cmpxchg_masked_and_branch2(ptr %ptr, i8 signext %cmp, i8 signext %v
351363
; RV64IA-ZACAS-NEXT: beq a1, a4, .LBB3_1
352364
; RV64IA-ZACAS-NEXT: # %bb.2: # %exit
353365
; RV64IA-ZACAS-NEXT: ret
366+
;
367+
; RV64IA-ZABHA-LABEL: cmpxchg_masked_and_branch2:
368+
; RV64IA-ZABHA: # %bb.0: # %entry
369+
; RV64IA-ZABHA-NEXT: .LBB3_1: # %do_cmpxchg
370+
; RV64IA-ZABHA-NEXT: # =>This Inner Loop Header: Depth=1
371+
; RV64IA-ZABHA-NEXT: mv a3, a1
372+
; RV64IA-ZABHA-NEXT: amocas.b.aqrl a3, a2, (a0)
373+
; RV64IA-ZABHA-NEXT: beq a3, a1, .LBB3_1
374+
; RV64IA-ZABHA-NEXT: # %bb.2: # %exit
375+
; RV64IA-ZABHA-NEXT: ret
354376
entry:
355377
br label %do_cmpxchg
356378
do_cmpxchg:

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