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[LoongArch] Add LSX intrinsic testcases
Depends on D155829 Reviewed By: SixWeining Differential Revision: https://reviews.llvm.org/D155834
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‎llvm/test/CodeGen/LoongArch/lsx/intrinsic-absd.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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declare <16 x i8> @llvm.loongarch.lsx.vabsd.b(<16 x i8>, <16 x i8>)
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define <16 x i8> @lsx_vabsd_b(<16 x i8> %va, <16 x i8> %vb) nounwind {
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; CHECK-LABEL: lsx_vabsd_b:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vabsd.b $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <16 x i8> @llvm.loongarch.lsx.vabsd.b(<16 x i8> %va, <16 x i8> %vb)
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ret <16 x i8> %res
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}
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declare <8 x i16> @llvm.loongarch.lsx.vabsd.h(<8 x i16>, <8 x i16>)
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define <8 x i16> @lsx_vabsd_h(<8 x i16> %va, <8 x i16> %vb) nounwind {
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; CHECK-LABEL: lsx_vabsd_h:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vabsd.h $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i16> @llvm.loongarch.lsx.vabsd.h(<8 x i16> %va, <8 x i16> %vb)
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ret <8 x i16> %res
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}
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declare <4 x i32> @llvm.loongarch.lsx.vabsd.w(<4 x i32>, <4 x i32>)
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define <4 x i32> @lsx_vabsd_w(<4 x i32> %va, <4 x i32> %vb) nounwind {
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; CHECK-LABEL: lsx_vabsd_w:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vabsd.w $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i32> @llvm.loongarch.lsx.vabsd.w(<4 x i32> %va, <4 x i32> %vb)
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ret <4 x i32> %res
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}
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declare <2 x i64> @llvm.loongarch.lsx.vabsd.d(<2 x i64>, <2 x i64>)
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define <2 x i64> @lsx_vabsd_d(<2 x i64> %va, <2 x i64> %vb) nounwind {
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; CHECK-LABEL: lsx_vabsd_d:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vabsd.d $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <2 x i64> @llvm.loongarch.lsx.vabsd.d(<2 x i64> %va, <2 x i64> %vb)
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ret <2 x i64> %res
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}
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declare <16 x i8> @llvm.loongarch.lsx.vabsd.bu(<16 x i8>, <16 x i8>)
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define <16 x i8> @lsx_vabsd_bu(<16 x i8> %va, <16 x i8> %vb) nounwind {
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; CHECK-LABEL: lsx_vabsd_bu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vabsd.bu $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <16 x i8> @llvm.loongarch.lsx.vabsd.bu(<16 x i8> %va, <16 x i8> %vb)
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ret <16 x i8> %res
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}
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declare <8 x i16> @llvm.loongarch.lsx.vabsd.hu(<8 x i16>, <8 x i16>)
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define <8 x i16> @lsx_vabsd_hu(<8 x i16> %va, <8 x i16> %vb) nounwind {
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; CHECK-LABEL: lsx_vabsd_hu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vabsd.hu $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i16> @llvm.loongarch.lsx.vabsd.hu(<8 x i16> %va, <8 x i16> %vb)
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ret <8 x i16> %res
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}
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declare <4 x i32> @llvm.loongarch.lsx.vabsd.wu(<4 x i32>, <4 x i32>)
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define <4 x i32> @lsx_vabsd_wu(<4 x i32> %va, <4 x i32> %vb) nounwind {
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; CHECK-LABEL: lsx_vabsd_wu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vabsd.wu $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i32> @llvm.loongarch.lsx.vabsd.wu(<4 x i32> %va, <4 x i32> %vb)
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ret <4 x i32> %res
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}
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declare <2 x i64> @llvm.loongarch.lsx.vabsd.du(<2 x i64>, <2 x i64>)
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define <2 x i64> @lsx_vabsd_du(<2 x i64> %va, <2 x i64> %vb) nounwind {
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; CHECK-LABEL: lsx_vabsd_du:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vabsd.du $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <2 x i64> @llvm.loongarch.lsx.vabsd.du(<2 x i64> %va, <2 x i64> %vb)
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ret <2 x i64> %res
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}

‎llvm/test/CodeGen/LoongArch/lsx/intrinsic-add.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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declare <16 x i8> @llvm.loongarch.lsx.vadd.b(<16 x i8>, <16 x i8>)
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define <16 x i8> @lsx_vadd_b(<16 x i8> %va, <16 x i8> %vb) nounwind {
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; CHECK-LABEL: lsx_vadd_b:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vadd.b $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <16 x i8> @llvm.loongarch.lsx.vadd.b(<16 x i8> %va, <16 x i8> %vb)
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ret <16 x i8> %res
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}
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declare <8 x i16> @llvm.loongarch.lsx.vadd.h(<8 x i16>, <8 x i16>)
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define <8 x i16> @lsx_vadd_h(<8 x i16> %va, <8 x i16> %vb) nounwind {
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; CHECK-LABEL: lsx_vadd_h:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vadd.h $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i16> @llvm.loongarch.lsx.vadd.h(<8 x i16> %va, <8 x i16> %vb)
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ret <8 x i16> %res
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}
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declare <4 x i32> @llvm.loongarch.lsx.vadd.w(<4 x i32>, <4 x i32>)
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define <4 x i32> @lsx_vadd_w(<4 x i32> %va, <4 x i32> %vb) nounwind {
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; CHECK-LABEL: lsx_vadd_w:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vadd.w $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i32> @llvm.loongarch.lsx.vadd.w(<4 x i32> %va, <4 x i32> %vb)
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ret <4 x i32> %res
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}
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declare <2 x i64> @llvm.loongarch.lsx.vadd.d(<2 x i64>, <2 x i64>)
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define <2 x i64> @lsx_vadd_d(<2 x i64> %va, <2 x i64> %vb) nounwind {
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; CHECK-LABEL: lsx_vadd_d:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vadd.d $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <2 x i64> @llvm.loongarch.lsx.vadd.d(<2 x i64> %va, <2 x i64> %vb)
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ret <2 x i64> %res
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}
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declare <2 x i64> @llvm.loongarch.lsx.vadd.q(<2 x i64>, <2 x i64>)
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define <2 x i64> @lsx_vadd_q(<2 x i64> %va, <2 x i64> %vb) nounwind {
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; CHECK-LABEL: lsx_vadd_q:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vadd.q $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <2 x i64> @llvm.loongarch.lsx.vadd.q(<2 x i64> %va, <2 x i64> %vb)
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ret <2 x i64> %res
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}

‎llvm/test/CodeGen/LoongArch/lsx/intrinsic-adda.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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declare <16 x i8> @llvm.loongarch.lsx.vadda.b(<16 x i8>, <16 x i8>)
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define <16 x i8> @lsx_vadda_b(<16 x i8> %va, <16 x i8> %vb) nounwind {
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; CHECK-LABEL: lsx_vadda_b:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vadda.b $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <16 x i8> @llvm.loongarch.lsx.vadda.b(<16 x i8> %va, <16 x i8> %vb)
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ret <16 x i8> %res
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}
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declare <8 x i16> @llvm.loongarch.lsx.vadda.h(<8 x i16>, <8 x i16>)
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define <8 x i16> @lsx_vadda_h(<8 x i16> %va, <8 x i16> %vb) nounwind {
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; CHECK-LABEL: lsx_vadda_h:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vadda.h $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i16> @llvm.loongarch.lsx.vadda.h(<8 x i16> %va, <8 x i16> %vb)
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ret <8 x i16> %res
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}
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declare <4 x i32> @llvm.loongarch.lsx.vadda.w(<4 x i32>, <4 x i32>)
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define <4 x i32> @lsx_vadda_w(<4 x i32> %va, <4 x i32> %vb) nounwind {
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; CHECK-LABEL: lsx_vadda_w:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vadda.w $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i32> @llvm.loongarch.lsx.vadda.w(<4 x i32> %va, <4 x i32> %vb)
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ret <4 x i32> %res
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}
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declare <2 x i64> @llvm.loongarch.lsx.vadda.d(<2 x i64>, <2 x i64>)
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define <2 x i64> @lsx_vadda_d(<2 x i64> %va, <2 x i64> %vb) nounwind {
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; CHECK-LABEL: lsx_vadda_d:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vadda.d $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <2 x i64> @llvm.loongarch.lsx.vadda.d(<2 x i64> %va, <2 x i64> %vb)
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ret <2 x i64> %res
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}

‎llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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declare <16 x i8> @llvm.loongarch.lsx.vaddi.bu(<16 x i8>, i32)
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define <16 x i8> @lsx_vaddi_bu(<16 x i8> %va) nounwind {
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; CHECK-LABEL: lsx_vaddi_bu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vaddi.bu $vr0, $vr0, 31
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; CHECK-NEXT: ret
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entry:
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%res = call <16 x i8> @llvm.loongarch.lsx.vaddi.bu(<16 x i8> %va, i32 31)
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ret <16 x i8> %res
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}
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declare <8 x i16> @llvm.loongarch.lsx.vaddi.hu(<8 x i16>, i32)
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define <8 x i16> @lsx_vaddi_hu(<8 x i16> %va) nounwind {
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; CHECK-LABEL: lsx_vaddi_hu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vaddi.hu $vr0, $vr0, 31
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i16> @llvm.loongarch.lsx.vaddi.hu(<8 x i16> %va, i32 31)
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ret <8 x i16> %res
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}
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declare <4 x i32> @llvm.loongarch.lsx.vaddi.wu(<4 x i32>, i32)
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define <4 x i32> @lsx_vaddi_wu(<4 x i32> %va) nounwind {
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; CHECK-LABEL: lsx_vaddi_wu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vaddi.wu $vr0, $vr0, 31
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i32> @llvm.loongarch.lsx.vaddi.wu(<4 x i32> %va, i32 31)
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ret <4 x i32> %res
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}
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declare <2 x i64> @llvm.loongarch.lsx.vaddi.du(<2 x i64>, i32)
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define <2 x i64> @lsx_vaddi_du(<2 x i64> %va) nounwind {
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; CHECK-LABEL: lsx_vaddi_du:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vaddi.du $vr0, $vr0, 31
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; CHECK-NEXT: ret
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entry:
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%res = call <2 x i64> @llvm.loongarch.lsx.vaddi.du(<2 x i64> %va, i32 31)
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ret <2 x i64> %res
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}

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