@@ -147,6 +147,7 @@ func TestGetContainerStats(t *testing.T) {
147147 intelRdtManager : & mockIntelRdtManager {
148148 stats : & intelrdt.Stats {
149149 L3CacheSchema : "L3:0=f;1=f0" ,
150+ MemBwSchema : "MB:0=20;1=70" ,
150151 },
151152 },
152153 }
@@ -160,14 +161,22 @@ func TestGetContainerStats(t *testing.T) {
160161 if stats .CgroupStats .MemoryStats .Usage .Usage != 1024 {
161162 t .Fatalf ("expected memory usage 1024 but recevied %d" , stats .CgroupStats .MemoryStats .Usage .Usage )
162163 }
163- if intelrdt .IsEnabled () {
164+ if intelrdt .IsCatEnabled () {
164165 if stats .IntelRdtStats == nil {
165166 t .Fatal ("intel rdt stats are nil" )
166167 }
167168 if stats .IntelRdtStats .L3CacheSchema != "L3:0=f;1=f0" {
168169 t .Fatalf ("expected L3CacheSchema L3:0=f;1=f0 but recevied %s" , stats .IntelRdtStats .L3CacheSchema )
169170 }
170171 }
172+ if intelrdt .IsMbaEnabled () {
173+ if stats .IntelRdtStats == nil {
174+ t .Fatal ("intel rdt stats are nil" )
175+ }
176+ if stats .IntelRdtStats .MemBwSchema != "MB:0=20;1=70" {
177+ t .Fatalf ("expected MemBwSchema MB:0=20;1=70 but recevied %s" , stats .IntelRdtStats .MemBwSchema )
178+ }
179+ }
171180}
172181
173182func TestGetContainerState (t * testing.T ) {
@@ -209,6 +218,7 @@ func TestGetContainerState(t *testing.T) {
209218 intelRdtManager : & mockIntelRdtManager {
210219 stats : & intelrdt.Stats {
211220 L3CacheSchema : "L3:0=f0;1=f" ,
221+ MemBwSchema : "MB:0=70;1=20" ,
212222 },
213223 path : expectedIntelRdtPath ,
214224 },
@@ -231,7 +241,7 @@ func TestGetContainerState(t *testing.T) {
231241 if memPath := paths ["memory" ]; memPath != expectedMemoryPath {
232242 t .Fatalf ("expected memory path %q but received %q" , expectedMemoryPath , memPath )
233243 }
234- if intelrdt .IsEnabled () {
244+ if intelrdt .IsCatEnabled () || intelrdt . IsMbaEnabled () {
235245 intelRdtPath := state .IntelRdtPath
236246 if intelRdtPath == "" {
237247 t .Fatal ("intel rdt path should not be empty" )
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