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libcontainer/intelrdt: add support for Schemata field
Implement support for the linux.intelRdt.schemata field of the spec. This allows management of the "schemata" file in the resctrl group in a generic way. Signed-off-by: Markus Lehtonen <[email protected]>
1 parent 3867f82 commit 4155321

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6 files changed

+82
-49
lines changed

6 files changed

+82
-49
lines changed

features.go

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,8 @@ var featuresCommand = cli.Command{
5656
Enabled: &t,
5757
},
5858
IntelRdt: &features.IntelRdt{
59-
Enabled: &t,
59+
Enabled: &t,
60+
Schemata: &t,
6061
},
6162
MountExtensions: &features.MountExtensions{
6263
IDMap: &features.IDMap{

libcontainer/configs/intelrdt.go

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,10 @@ type IntelRdt struct {
44
// The identity for RDT Class of Service
55
ClosID string `json:"closID,omitempty"`
66

7+
// Schemata is a generic field to specify schemata file in the resctrl
8+
// filesystem. Each element represents one line written to the schemata file.
9+
Schemata []string `json:"schemata,omitempty"`
10+
711
// The schema for L3 cache id and capacity bitmask (CBM)
812
// Format: "L3:<cache_id0>=<cbm0>;<cache_id1>=<cbm1>;..."
913
L3CacheSchema string `json:"l3_cache_schema,omitempty"`

libcontainer/intelrdt/intelrdt.go

Lines changed: 12 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -326,16 +326,6 @@ func getIntelRdtParamString(path, file string) (string, error) {
326326
return string(bytes.TrimSpace(contents)), nil
327327
}
328328

329-
func writeFile(dir, file, data string) error {
330-
if dir == "" {
331-
return fmt.Errorf("no such directory for %s", file)
332-
}
333-
if err := os.WriteFile(filepath.Join(dir, file), []byte(data+"\n"), 0o600); err != nil {
334-
return newLastCmdError(fmt.Errorf("intelrdt: unable to write %v: %w", data, err))
335-
}
336-
return nil
337-
}
338-
339329
// Get the read-only L3 cache information
340330
func getL3CacheInfo() (*L3CacheInfo, error) {
341331
l3CacheInfo := &L3CacheInfo{}
@@ -462,11 +452,11 @@ func (m *Manager) Apply(pid int) (err error) {
462452
m.mu.Lock()
463453
defer m.mu.Unlock()
464454

465-
if m.config.IntelRdt.ClosID != "" && m.config.IntelRdt.L3CacheSchema == "" && m.config.IntelRdt.MemBwSchema == "" {
455+
if m.config.IntelRdt.ClosID != "" && m.config.IntelRdt.L3CacheSchema == "" && m.config.IntelRdt.MemBwSchema == "" && len(m.config.IntelRdt.Schemata) == 0 {
466456
// Check that the CLOS exists, i.e. it has been pre-configured to
467457
// conform with the runtime spec
468458
if _, err := os.Stat(path); err != nil {
469-
return fmt.Errorf("clos dir not accessible (must be pre-created when l3CacheSchema and memBwSchema are empty): %w", err)
459+
return fmt.Errorf("clos dir not accessible (must be pre-created when schemata, l3CacheSchema and memBwSchema are empty): %w", err)
470460
}
471461
}
472462

@@ -637,35 +627,24 @@ func (m *Manager) Set(container *configs.Config) error {
637627
// For example, on a two-socket machine, the schema line could be
638628
// "MB:0=5000;1=7000" which means 5000 MBps memory bandwidth limit on
639629
// socket 0 and 7000 MBps memory bandwidth limit on socket 1.
640-
if container.IntelRdt != nil {
641-
path := m.GetPath()
642-
l3CacheSchema := container.IntelRdt.L3CacheSchema
643-
memBwSchema := container.IntelRdt.MemBwSchema
644-
630+
if r := container.IntelRdt; r != nil {
645631
// TODO: verify that l3CacheSchema and/or memBwSchema match the
646632
// existing schemata if ClosID has been specified. This is a more
647633
// involved than reading the file and doing plain string comparison as
648634
// the value written in does not necessarily match what gets read out
649635
// (leading zeros, cache id ordering etc).
650-
651-
// Write a single joint schema string to schemata file
652-
if l3CacheSchema != "" && memBwSchema != "" {
653-
if err := writeFile(path, "schemata", l3CacheSchema+"\n"+memBwSchema); err != nil {
654-
return err
655-
}
656-
}
657-
658-
// Write only L3 cache schema string to schemata file
659-
if l3CacheSchema != "" && memBwSchema == "" {
660-
if err := writeFile(path, "schemata", l3CacheSchema); err != nil {
661-
return err
636+
var schemata strings.Builder
637+
for _, s := range append([]string{r.L3CacheSchema, r.MemBwSchema}, r.Schemata...) {
638+
if s != "" {
639+
schemata.WriteString(s)
640+
schemata.WriteString("\n")
662641
}
663642
}
664643

665-
// Write only memory bandwidth schema string to schemata file
666-
if l3CacheSchema == "" && memBwSchema != "" {
667-
if err := writeFile(path, "schemata", memBwSchema); err != nil {
668-
return err
644+
if schemata.Len() > 0 {
645+
path := filepath.Join(m.GetPath(), "schemata")
646+
if err := os.WriteFile(path, []byte(schemata.String()), 0o600); err != nil {
647+
return newLastCmdError(fmt.Errorf("intelrdt: unable to write %q: %w", schemata.String(), err))
669648
}
670649
}
671650
}

libcontainer/intelrdt/intelrdt_test.go

Lines changed: 63 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -37,18 +37,76 @@ func TestIntelRdtSet(t *testing.T) {
3737
},
3838
schemataAfter: []string{"MB:0=9000;1=4000"},
3939
},
40+
{
41+
name: "L3 and MemBw",
42+
config: &configs.IntelRdt{
43+
L3CacheSchema: "L3:0=f0;1=f",
44+
MemBwSchema: "MB:0=9000;1=4000",
45+
},
46+
schemataAfter: []string{
47+
"L3:0=f0;1=f",
48+
"MB:0=9000;1=4000",
49+
},
50+
},
51+
{
52+
name: "Schemata",
53+
config: &configs.IntelRdt{
54+
Schemata: []string{
55+
"L3CODE:0=ff;1=ff",
56+
"L3DATA:0=f;1=f0",
57+
},
58+
},
59+
schemataAfter: []string{
60+
"L3CODE:0=ff;1=ff",
61+
"L3DATA:0=f;1=f0",
62+
},
63+
},
64+
{
65+
name: "Schemata and L3",
66+
config: &configs.IntelRdt{
67+
L3CacheSchema: "L3:0=f0;1=f",
68+
Schemata: []string{"L2:0=ff00;1=ff"},
69+
},
70+
schemataAfter: []string{
71+
"L3:0=f0;1=f",
72+
"L2:0=ff00;1=ff",
73+
},
74+
},
75+
{
76+
name: "Schemata and MemBw",
77+
config: &configs.IntelRdt{
78+
MemBwSchema: "MB:0=2000;1=4000",
79+
Schemata: []string{"L3:0=ff;1=ff"},
80+
},
81+
schemataAfter: []string{
82+
"MB:0=2000;1=4000",
83+
"L3:0=ff;1=ff",
84+
},
85+
},
86+
{
87+
name: "Schemata, L3 and MemBw",
88+
config: &configs.IntelRdt{
89+
L3CacheSchema: "L3:0=80;1=7f",
90+
MemBwSchema: "MB:0=2000;1=4000",
91+
Schemata: []string{
92+
"L2:0=ff00;1=ff",
93+
"L3:0=c0;1=3f",
94+
},
95+
},
96+
schemataAfter: []string{
97+
"L3:0=80;1=7f",
98+
"MB:0=2000;1=4000",
99+
"L2:0=ff00;1=ff",
100+
"L3:0=c0;1=3f",
101+
},
102+
},
40103
}
41104

42105
for _, tc := range tcs {
43106
t.Run(tc.name, func(t *testing.T) {
44107
helper := NewIntelRdtTestUtil(t)
45108
helper.config.IntelRdt = tc.config
46109

47-
helper.writeFileContents(map[string]string{
48-
/* Common initial value for all test cases */
49-
"schemata": "MB:0=100\nL3:0=ffff\nL2:0=ffffffff\n",
50-
})
51-
52110
intelrdt := newManager(helper.config, "", helper.IntelRdtPath)
53111
if err := intelrdt.Set(helper.config); err != nil {
54112
t.Fatal(err)

libcontainer/intelrdt/util_test.go

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -40,13 +40,3 @@ func NewIntelRdtTestUtil(t *testing.T) *intelRdtTestUtil {
4040
}
4141
return &intelRdtTestUtil{config: config, IntelRdtPath: testIntelRdtPath, t: t}
4242
}
43-
44-
// Write the specified contents on the mock of the specified Intel RDT "resource control" files
45-
func (c *intelRdtTestUtil) writeFileContents(fileContents map[string]string) {
46-
for file, contents := range fileContents {
47-
err := writeFile(c.IntelRdtPath, file, contents)
48-
if err != nil {
49-
c.t.Fatal(err)
50-
}
51-
}
52-
}

libcontainer/specconv/spec_linux.go

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -463,6 +463,7 @@ func CreateLibcontainerConfig(opts *CreateOpts) (*configs.Config, error) {
463463
if spec.Linux.IntelRdt != nil {
464464
config.IntelRdt = &configs.IntelRdt{
465465
ClosID: spec.Linux.IntelRdt.ClosID,
466+
Schemata: spec.Linux.IntelRdt.Schemata,
466467
L3CacheSchema: spec.Linux.IntelRdt.L3CacheSchema,
467468
MemBwSchema: spec.Linux.IntelRdt.MemBwSchema,
468469
}

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