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libcontainer: intelrdt: add test cases for Intel RDT/MBA
Signed-off-by: Xiaochen Shen <[email protected]>
1 parent 13f06db commit 4aea0b3

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2 files changed

+51
-3
lines changed

2 files changed

+51
-3
lines changed

libcontainer/container_linux_test.go

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -147,6 +147,7 @@ func TestGetContainerStats(t *testing.T) {
147147
intelRdtManager: &mockIntelRdtManager{
148148
stats: &intelrdt.Stats{
149149
L3CacheSchema: "L3:0=f;1=f0",
150+
MemBwSchema: "MB:0=20;1=70",
150151
},
151152
},
152153
}
@@ -160,14 +161,22 @@ func TestGetContainerStats(t *testing.T) {
160161
if stats.CgroupStats.MemoryStats.Usage.Usage != 1024 {
161162
t.Fatalf("expected memory usage 1024 but recevied %d", stats.CgroupStats.MemoryStats.Usage.Usage)
162163
}
163-
if intelrdt.IsEnabled() {
164+
if intelrdt.IsCatEnabled() {
164165
if stats.IntelRdtStats == nil {
165166
t.Fatal("intel rdt stats are nil")
166167
}
167168
if stats.IntelRdtStats.L3CacheSchema != "L3:0=f;1=f0" {
168169
t.Fatalf("expected L3CacheSchema L3:0=f;1=f0 but recevied %s", stats.IntelRdtStats.L3CacheSchema)
169170
}
170171
}
172+
if intelrdt.IsMbaEnabled() {
173+
if stats.IntelRdtStats == nil {
174+
t.Fatal("intel rdt stats are nil")
175+
}
176+
if stats.IntelRdtStats.MemBwSchema != "MB:0=20;1=70" {
177+
t.Fatalf("expected MemBwSchema MB:0=20;1=70 but recevied %s", stats.IntelRdtStats.MemBwSchema)
178+
}
179+
}
171180
}
172181

173182
func TestGetContainerState(t *testing.T) {
@@ -209,6 +218,7 @@ func TestGetContainerState(t *testing.T) {
209218
intelRdtManager: &mockIntelRdtManager{
210219
stats: &intelrdt.Stats{
211220
L3CacheSchema: "L3:0=f0;1=f",
221+
MemBwSchema: "MB:0=70;1=20",
212222
},
213223
path: expectedIntelRdtPath,
214224
},
@@ -231,7 +241,7 @@ func TestGetContainerState(t *testing.T) {
231241
if memPath := paths["memory"]; memPath != expectedMemoryPath {
232242
t.Fatalf("expected memory path %q but received %q", expectedMemoryPath, memPath)
233243
}
234-
if intelrdt.IsEnabled() {
244+
if intelrdt.IsCatEnabled() || intelrdt.IsMbaEnabled() {
235245
intelRdtPath := state.IntelRdtPath
236246
if intelRdtPath == "" {
237247
t.Fatal("intel rdt path should not be empty")

libcontainer/intelrdt/intelrdt_test.go

Lines changed: 39 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ import (
88
)
99

1010
func TestIntelRdtSetL3CacheSchema(t *testing.T) {
11-
if !IsEnabled() {
11+
if !IsCatEnabled() {
1212
return
1313
}
1414

@@ -44,3 +44,41 @@ func TestIntelRdtSetL3CacheSchema(t *testing.T) {
4444
t.Fatal("Got the wrong value, set 'schemata' failed.")
4545
}
4646
}
47+
48+
func TestIntelRdtSetMemBwSchema(t *testing.T) {
49+
if !IsMbaEnabled() {
50+
return
51+
}
52+
53+
helper := NewIntelRdtTestUtil(t)
54+
defer helper.cleanup()
55+
56+
const (
57+
memBwSchemaBefore = "MB:0=20;1=70"
58+
memBwSchemeAfter = "MB:0=70;1=20"
59+
)
60+
61+
helper.writeFileContents(map[string]string{
62+
"schemata": memBwSchemaBefore + "\n",
63+
})
64+
65+
helper.IntelRdtData.config.IntelRdt.MemBwSchema = memBwSchemeAfter
66+
intelrdt := &IntelRdtManager{
67+
Config: helper.IntelRdtData.config,
68+
Path: helper.IntelRdtPath,
69+
}
70+
if err := intelrdt.Set(helper.IntelRdtData.config); err != nil {
71+
t.Fatal(err)
72+
}
73+
74+
tmpStrings, err := getIntelRdtParamString(helper.IntelRdtPath, "schemata")
75+
if err != nil {
76+
t.Fatalf("Failed to parse file 'schemata' - %s", err)
77+
}
78+
values := strings.Split(tmpStrings, "\n")
79+
value := values[0]
80+
81+
if value != memBwSchemeAfter {
82+
t.Fatal("Got the wrong value, set 'schemata' failed.")
83+
}
84+
}

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