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libcontainer: intelrdt: add update command support for Intel RDT/MBA
Signed-off-by: Xiaochen Shen <[email protected]>
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1 file changed

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update.go

Lines changed: 17 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -118,6 +118,10 @@ other options are ignored.
118118
Name: "l3-cache-schema",
119119
Usage: "The string of Intel RDT/CAT L3 cache schema",
120120
},
121+
cli.StringFlag{
122+
Name: "mem-bw-schema",
123+
Usage: "The string of Intel RDT/MBA memory bandwidth schema",
124+
},
121125
},
122126
Action: func(context *cli.Context) error {
123127
if err := checkArgs(context, 1, exactArgs); err != nil {
@@ -260,12 +264,18 @@ other options are ignored.
260264
config.Cgroups.Resources.MemorySwap = *r.Memory.Swap
261265
config.Cgroups.Resources.PidsLimit = r.Pids.Limit
262266

263-
// Update Intel RDT/CAT
264-
if val := context.String("l3-cache-schema"); val != "" {
265-
if !intelrdt.IsCatEnabled() {
266-
return fmt.Errorf("Intel RDT: l3 cache schema is not enabled")
267-
}
267+
// Update Intel RDT
268+
l3CacheSchema := context.String("l3-cache-schema")
269+
memBwSchema := context.String("mem-bw-schema")
270+
if l3CacheSchema != "" && !intelrdt.IsCatEnabled() {
271+
return fmt.Errorf("Intel RDT/CAT: l3 cache schema is not enabled")
272+
}
273+
274+
if memBwSchema != "" && !intelrdt.IsMbaEnabled() {
275+
return fmt.Errorf("Intel RDT/MBA: memory bandwidth schema is not enabled")
276+
}
268277

278+
if l3CacheSchema != "" || memBwSchema != "" {
269279
// If intelRdt is not specified in original configuration, we just don't
270280
// Apply() to create intelRdt group or attach tasks for this container.
271281
// In update command, we could re-enable through IntelRdtManager.Apply()
@@ -285,7 +295,8 @@ other options are ignored.
285295
return err
286296
}
287297
}
288-
config.IntelRdt.L3CacheSchema = val
298+
config.IntelRdt.L3CacheSchema = l3CacheSchema
299+
config.IntelRdt.MemBwSchema = memBwSchema
289300
}
290301

291302
return container.Set(config)

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