@@ -148,6 +148,7 @@ func TestGetContainerStats(t *testing.T) {
148148 intelRdtManager : & mockIntelRdtManager {
149149 stats : & intelrdt.Stats {
150150 L3CacheSchema : "L3:0=f;1=f0" ,
151+ MemBwSchema : "MB:0=20;1=70" ,
151152 },
152153 },
153154 }
@@ -161,14 +162,22 @@ func TestGetContainerStats(t *testing.T) {
161162 if stats .CgroupStats .MemoryStats .Usage .Usage != 1024 {
162163 t .Fatalf ("expected memory usage 1024 but received %d" , stats .CgroupStats .MemoryStats .Usage .Usage )
163164 }
164- if intelrdt .IsEnabled () {
165+ if intelrdt .IsCatEnabled () {
165166 if stats .IntelRdtStats == nil {
166167 t .Fatal ("intel rdt stats are nil" )
167168 }
168169 if stats .IntelRdtStats .L3CacheSchema != "L3:0=f;1=f0" {
169170 t .Fatalf ("expected L3CacheSchema L3:0=f;1=f0 but recevied %s" , stats .IntelRdtStats .L3CacheSchema )
170171 }
171172 }
173+ if intelrdt .IsMbaEnabled () {
174+ if stats .IntelRdtStats == nil {
175+ t .Fatal ("intel rdt stats are nil" )
176+ }
177+ if stats .IntelRdtStats .MemBwSchema != "MB:0=20;1=70" {
178+ t .Fatalf ("expected MemBwSchema MB:0=20;1=70 but recevied %s" , stats .IntelRdtStats .MemBwSchema )
179+ }
180+ }
172181}
173182
174183func TestGetContainerState (t * testing.T ) {
@@ -210,6 +219,7 @@ func TestGetContainerState(t *testing.T) {
210219 intelRdtManager : & mockIntelRdtManager {
211220 stats : & intelrdt.Stats {
212221 L3CacheSchema : "L3:0=f0;1=f" ,
222+ MemBwSchema : "MB:0=70;1=20" ,
213223 },
214224 path : expectedIntelRdtPath ,
215225 },
@@ -232,7 +242,7 @@ func TestGetContainerState(t *testing.T) {
232242 if memPath := paths ["memory" ]; memPath != expectedMemoryPath {
233243 t .Fatalf ("expected memory path %q but received %q" , expectedMemoryPath , memPath )
234244 }
235- if intelrdt .IsEnabled () {
245+ if intelrdt .IsCatEnabled () || intelrdt . IsMbaEnabled () {
236246 intelRdtPath := state .IntelRdtPath
237247 if intelRdtPath == "" {
238248 t .Fatal ("intel rdt path should not be empty" )
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