@@ -476,6 +476,91 @@ The following parameters can be specified to setup the controller:
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}
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```
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+ ## <a name =" configLinuxIntelRdt " />IntelRdt
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+
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+ Intel platforms with new Xeon CPU support Intel Resource Director Technology
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+ (RDT). Cache Allocation Technology (CAT) is a sub-feature of RDT, which
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+ currently supports L3 cache resource allocation.
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+
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+ This feature provides a way for the software to restrict cache allocation to a
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+ defined 'subset' of L3 cache which may be overlapping with other 'subsets'.
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+ The different subsets are identified by class of service (CLOS) and each CLOS
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+ has a capacity bitmask (CBM).
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+
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+ In Linux kernel, it is exposed via "resource control" filesystem, which is a
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+ "cgroup-like" interface.
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+
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+ Comparing with cgroups, it has similar process management lifecycle and
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+ interfaces in a container. But unlike cgroups' hierarchy, it has single level
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+ filesystem layout.
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+
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+ Intel RDT "resource control" filesystem hierarchy:
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+ ```
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+ mount -t resctrl resctrl /sys/fs/resctrl
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+ tree /sys/fs/resctrl
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+ /sys/fs/resctrl/
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+ |-- info
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+ | |-- L3
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+ | |-- cbm_mask
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+ | |-- min_cbm_bits
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+ | |-- num_closids
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+ |-- cpus
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+ |-- schemata
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+ |-- tasks
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+ |-- <container_id>
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+ |-- cpus
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+ |-- schemata
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+ |-- tasks
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+
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+ ```
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+
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+ For containers, we can make use of ` tasks ` and ` schemata ` configuration for
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+ L3 cache resource constraints if hardware and kernel support Intel RDT/CAT.
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+
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+ The file ` tasks ` has a list of tasks that belongs to this group (e.g.,
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+ <container_id>" group). Tasks can be added to a group by writing the task ID
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+ to the "tasks" file (which will automatically remove them from the previous
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+ group to which they belonged). New tasks created by fork(2) and clone(2) are
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+ added to the same group as their parent. If a pid is not in any sub group, it
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+ is in root group.
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+
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+ The file ` schemata ` has allocation masks/values for L3 cache on each socket,
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+ which contains L3 cache id and capacity bitmask (CBM).
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+ ```
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+ Format: "L3:<cache_id0>=<cbm0>;<cache_id1>=<cbm1>;..."
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+ ```
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+ For example, on a two-socket machine, L3's schema line could be ` L3:0=ff;1=c0 `
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+ Which means L3 cache id 0's CBM is 0xff, and L3 cache id 1's CBM is 0xc0.
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+
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+ The valid L3 cache CBM is a * contiguous bits set* and number of bits that can
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+ be set is less than the max bit. The max bits in the CBM is varied among
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+ supported Intel Xeon platforms. In Intel RDT "resource control" filesystem
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+ layout, the CBM in a group should be a subset of the CBM in root. Kernel will
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+ check if it is valid when writing. e.g., 0xfffff in root indicates the max bits
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+ of CBM is 20 bits, which mapping to entire L3 cache capacity. Some valid CBM
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+ values to set in a group: 0xf, 0xf0, 0x3ff, 0x1f00 and etc.
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+
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+ ** ` intelRdt ` ** (object, OPTIONAL) represents the L3 cache resource constraints in Intel Xeon platforms.
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+
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+ For more information, see [ Intel RDT/CAT kernel interface] [ intel-rdt-cat-kernel-interface ] .
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+
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+ The following parameters can be specified for the container:
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+
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+ * ** ` l3CacheSchema ` ** * (string, OPTIONAL)* - specifies the schema for L3 cache id and capacity bitmask (CBM)
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+
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+ ###### Example
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+ ``` json
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+ There are two L3 caches in the two-socket machine, the default CBM is 0xfffff
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+ and the max CBM length is 20 bits. This configuration assigns 4/5 of L3 cache
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+ id 0 and the whole L3 cache id 1 for the container:
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+
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+ "linux" : {
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+ "intelRdt" : {
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+ "l3CacheSchema" : " L3:0=ffff0;1=fffff"
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+ }
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+ }
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+ ```
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+
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## <a name =" configLinuxSysctl " />Sysctl
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** ` sysctl ` ** (object, OPTIONAL) allows kernel parameters to be modified at runtime for the container.
@@ -638,3 +723,4 @@ The values MUST be absolute paths in the [container namespace][container-namespa
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[ tty.4 ] : http://man7.org/linux/man-pages/man4/tty.4.html
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[ zero.4 ] : http://man7.org/linux/man-pages/man4/zero.4.html
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[ user-namespaces ] : http://man7.org/linux/man-pages/man7/user_namespaces.7.html
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+ [ intel-rdt-cat-kernel-interface ] : https://www.kernel.org/doc/Documentation/x86/intel_rdt_ui.txt
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