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Add support for Intel Resource Director Technology (RDT) /
Memory Bandwidth Allocation (MBA). Add memory bandwidth resource
constraints in Linux-specific configuration.
In this PR, the spec for memory bandwidth (memBwSchema) keeps
the same format as existed spec for L3 cache (l3CacheSchema)
for consistency and compatibility in runtime-spec 1.x.
Example:
"linux": {
"intelRdt": {
"l3CacheSchema": "L3:0=7f0;1=1f",
"memBwSchema": "MB:0=20;1=70"
}
}
This is the prerequisite of this runc proposal:
opencontainers/runc#1596
For more information about Intel RDT/MBA, please refer to:
opencontainers/runc#1596
Signed-off-by: Xiaochen Shen <[email protected]>
Copy file name to clipboardExpand all lines: config-linux.md
+12-5Lines changed: 12 additions & 5 deletions
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@@ -466,19 +466,26 @@ The following parameters can be specified to set up the controller:
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The following parameters can be specified for the container:
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***`l3CacheSchema`***(string, OPTIONAL)* - specifies the schema for L3 cache id and capacity bitmask (CBM).
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If `l3CacheSchema` is set, runtimes MUST write the value to the `schemata` file in the `<container-id>` directory discussed in `intelRdt`.
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***`memBwSchema`***(string, OPTIONAL)* - specifies the schema of memory bandwidth percentage per L3 cache id.
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If `l3CacheSchema` is not set, runtimes MUST NOT write to `schemata` files in any `resctrl` pseudo-filesystems.
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If both `l3CacheSchema` and `memBwSchema` are set, runtimes MUST write the value to the `schemata` file in the `<container-id>` directory discussed in `intelRdt`.
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If either `l3CacheSchema` or `memBwSchema` is set, runtimes MUST write the value to the `schemata` file in the `<container-id>` directory discussed in `intelRdt`.
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If neither `l3CacheSchema` nor `memBwSchema` is set, runtimes MUST NOT write to `schemata` files in any `resctrl` pseudo-filesystems.
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### Example
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Consider a two-socket machine with two L3 caches where the default CBM is 0xfffff and the max CBM length is 20 bits.
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Tasks inside the container only have access to the "upper" 80% of L3 cache id 0 and the "lower" 50% L3 cache id 1:
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Consider a two-socket machine with two L3 caches where the default CBM is 0x7ff and the max CBM length is 11 bits,
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and minimum memory bandwidth of 10% with a memory bandwidth granularity of 10%.
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Tasks inside the container only have access to the "upper" 7/11 of L3 cache on socket 0 and the "lower" 5/11 L3 cache on socket 1,
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and may use a maximum memory bandwidth of 20% on socket 0 and 70% on socket 1.
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