Monitor instruction flowing into the pipeline through ILA on FPGA

[gm-openchip]

Hi,
I’m looking to monitor instruction opcodes as they enter the processor pipeline using an ILA on an FPGA dev board.
Here asking what would be the best candidate signals and busses to tap into for this purpose.

I was thinking of picking instruction_o out of decoder.sv -->

cva6/core/decoder.sv

Line 88 in a9190fd

output scoreboard_entry_t instruction_o,

Or maybe also the internal instr -->

cva6/core/decoder.sv

Line 106 in a9190fd

assign instr = riscv::instruction_t'(instruction_i);

Any suggestion?
Also, I understand that those are in-order issued instruction to the processor pipeline execution stage, but the wb of the instructions can be ooo, so is there an equivalent of the instruction opcodes as they are actually being write-back by the cpu itself? Is there any way to tap that opcodes as well into the ILA?

Thanks!