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Merge pull request #788 from jordancarlin/main
New test framework
2 parents 7ff9073 + 578fad1 commit bfc6044

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.gitignore

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@@ -53,3 +53,7 @@ testplans/Vx.csv
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wkdir
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fcov_ucdb
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*.trace
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*.tracelist
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*.mk

.pre-commit-config.yaml

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@@ -30,7 +30,7 @@ repos:
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# Ruff python linter
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- repo: https://github.com/astral-sh/ruff-pre-commit
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rev: v0.12.10
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rev: v0.12.11
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hooks:
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# Run the linter.
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- id: ruff-check

.python-version

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3.12

Makefile

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@@ -30,11 +30,6 @@ UNPRIVOBJECTS = $(UNPRIV_SOURCES:.$(SRCEXT)=.$(OBJEXT))
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# Main targets
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all: unpriv priv
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Vx : riscv-arch-Vx8 riscv-arch-Vx16 riscv-arch-Vx32 riscv-arch-Vx64
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Vls : riscv-arch-Vls8 riscv-arch-Vls16 riscv-arch-Vls32 riscv-arch-Vls64
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Vf : riscv-arch-Vf16 riscv-arch-Vf32 riscv-arch-Vf64
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V : Vx Vls Vf
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unpriv: testgen
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$(MAKE) $(UNPRIVOBJECTS)
@@ -48,21 +43,8 @@ covergroupgen: bin/covergroupgen.py
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testgen: covergroupgen bin/vector-testgen-unpriv.py bin/combinetests.py bin/testgen.py
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bin/testgen.py
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bin/vector-testgen-unpriv.py
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# bin/vector-testgen-unpriv.py
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rm -rf ${TESTDIR}/rv32/E ${TESTDIR}/rv64/E # E tests are not used in the regular (I) suite
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# bin/combinetests.py
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riscv-arch: testgen
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cp -r ${TESTDIR}/rv32/* ${WALLY}/addins/cvw-riscv-arch-test/riscv-test-suite/rv32i/
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cp -r ${TESTDIR}/rv64/* ${WALLY}/addins/cvw-riscv-arch-test/riscv-test-suite/rv64i/
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riscv-arch-%: testgen
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rm -rf ${WALLY}/addins/cvw-riscv-arch-test/riscv-test-suite/rv32i/$*
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rm -rf ${WALLY}/addins/cvw-riscv-arch-test/riscv-test-suite/rv64i/$*
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mkdir -p ${WALLY}/addins/cvw-riscv-arch-test/riscv-test-suite/rv32i/$*
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mkdir -p ${WALLY}/addins/cvw-riscv-arch-test/riscv-test-suite/rv64i/$*
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cp -r ${TESTDIR}/rv32/$* ${WALLY}/addins/cvw-riscv-arch-test/riscv-test-suite/rv32i/$*
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cp -r ${TESTDIR}/rv64/$* ${WALLY}/addins/cvw-riscv-arch-test/riscv-test-suite/rv64i/$*
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privheaders: bin/csrtests.py bin/illegalinstrtests.py | $(PRIVHEADERSDIR)
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bin/csrtests.py
@@ -108,7 +90,7 @@ sim:
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interrupts:
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rm -f ${WALLY}/sim/questa/fcov_ucdb/*
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cd ${WALLY}/tests/riscof/riscof_work/cvw-arch64/privileged/interrupts/src/InterruptsM.S/ref;riscv64-unknown-elf-gcc -march=rv64i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T ${WALLY}/tests/riscof/sail_cSim/env/link.ld -I ${WALLY}/tests/riscof/sail_cSim/env/ -I ${WALLY}/addins/cvw-riscv-arch-test/riscv-test-suite/env -mabi=lp64 ${WALLY}/addins/cvw-riscv-arch-test/riscv-test-suite/privileged/interrupts/src/InterruptsM.S -o ref.elf -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True -Drvtest_dtrap_routine=True -DTEST_CASE_1=True -DXLEN=64
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cd ${WALLY}/tests/riscof/riscof_work/cvw-arch64/privileged/interrupts/src/InterruptsM.S/ref;riscv64-unknown-elf-gcc -march=rv64i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T ${WALLY}/tests/riscof/sail_cSim/env/link.ld -I ${WALLY}/tests/riscof/sail_cSim/env/ -I ${WALLY}/addins/cvw-riscv-arch-test/riscv-test-suite/env -mabi=lp64 ${WALLY}/addins/cvw-riscv-arch-test/riscv-test-suite/privileged/interrupts/src/InterruptsM.S -o ref.elf -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True -Drvtest_dtrap_routine=True -DTEST_CASE_1=True -DXLEN=64
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cd ${WALLY}/tests/riscof/riscof_work/cvw-arch64/privileged/interrupts/src/InterruptsS_Mmode.S/ref;riscv64-unknown-elf-gcc -march=rv64i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T ${WALLY}/tests/riscof/sail_cSim/env/link.ld -I ${WALLY}/tests/riscof/sail_cSim/env/ -I ${WALLY}/addins/cvw-riscv-arch-test/riscv-test-suite/env -mabi=lp64 ${WALLY}/addins/cvw-riscv-arch-test/riscv-test-suite/privileged/interrupts/src/InterruptsS_Mmode.S -o ref.elf -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True -Drvtest_dtrap_routine=True -DTEST_CASE_1=True -DXLEN=64
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cd ${WALLY}/tests/riscof/riscof_work/cvw-arch64/privileged/interrupts/src/InterruptsS_Smode.S/ref;riscv64-unknown-elf-gcc -march=rv64i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T ${WALLY}/tests/riscof/sail_cSim/env/link.ld -I ${WALLY}/tests/riscof/sail_cSim/env/ -I ${WALLY}/addins/cvw-riscv-arch-test/riscv-test-suite/env -mabi=lp64 ${WALLY}/addins/cvw-riscv-arch-test/riscv-test-suite/privileged/interrupts/src/InterruptsS_Smode.S -o ref.elf -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True -Drvtest_dtrap_routine=True -DTEST_CASE_1=True -DXLEN=64
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cd ${WALLY}/tests/riscof/riscof_work/cvw-arch64/privileged/interrupts/src/InterruptsS_Umode.S/ref;riscv64-unknown-elf-gcc -march=rv64i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T ${WALLY}/tests/riscof/sail_cSim/env/link.ld -I ${WALLY}/tests/riscof/sail_cSim/env/ -I ${WALLY}/addins/cvw-riscv-arch-test/riscv-test-suite/env -mabi=lp64 ${WALLY}/addins/cvw-riscv-arch-test/riscv-test-suite/privileged/interrupts/src/InterruptsS_Umode.S -o ref.elf -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True -Drvtest_dtrap_routine=True -DTEST_CASE_1=True -DXLEN=64
@@ -154,8 +136,6 @@ $(SRCDIR64) $(SRCDIR32) $(PRIVDIR) $(PRIVHEADERSDIR) $(PRIVDIR64) $(PRIVDIR32) $
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clean:
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rm -rf fcov/unpriv/*
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rm -rf $(SRCDIR64) $(SRCDIR32) $(PRIVHEADERSDIR) $(PRIVDIR64) $(PRIVDIR32) $(WORK)
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rm -rf ${WALLY}/addins/cvw-riscv-arch-test/riscv-test-suite/rv32i/*
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rm -rf ${WALLY}/addins/cvw-riscv-arch-test/riscv-test-suite/rv64i/*
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lint:
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uvx ruff check

bin/makefilegen.py

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bin/testgen.py

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@@ -30,33 +30,34 @@ def insertTemplate(name, is_custom=False):
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ext_parts = re.findall(r'Z[a-z]+|[A-Z]', extension)
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ext_parts_no_I = [ext for ext in ext_parts if ext != "I"]
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if 'D' in ext_parts_no_I or 'Zcd' in ext_parts_no_I:
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ext_parts_no_I = ['D']+ext_parts_no_I
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ext_parts_no_I = ['D']+ext_parts_no_I
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if 'M' in ext_parts_no_I:
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ext_parts_no_I = ['M']+ext_parts_no_I
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if 'Zalrsc' in ext_parts_no_I: #Adding this until gcc15 is updated bc currently no support for this extension
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ext_parts_no_I = ['A']#+ext_parts_no_I
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if 'Zaamo' in ext_parts_no_I: #Adding this until gcc15 is updated bc currently no support for this extension
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ext_parts_no_I = ['A']#+ext_parts_no_I
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ext_parts_no_I = ['M']+ext_parts_no_I
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if 'F' in ext_parts_no_I or any('f' in ext for ext in ext_parts_no_I):
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ext_parts_no_I = ['F']+ext_parts_no_I
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ext_parts_no_I = ['F']+ext_parts_no_I
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if len(ext_parts_no_I) != 0:
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if ext_parts_no_I[-1] == 'D':
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ext_parts_no_I = ext_parts_no_I[:-1]
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if ext_parts_no_I[-1] == 'M':
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ext_parts_no_I = ext_parts_no_I[:-1]
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if ext_parts_no_I[-1] == 'F':
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ext_parts_no_I = ext_parts_no_I[:-1]
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#ISAEXT = f"RV{xlen}I{''.join(ext_parts_no_I)}"
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raw_ISAEXT = f"RV{xlen}I{''.join(ext_parts_no_I)}"
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ISAEXT = insert_all_Z_underscores_after_first(raw_ISAEXT)
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# Construct the regex part
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ext_regex = ".*I.*" + "".join([f"{ext}.*" for ext in ext_parts_no_I])
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test_case_line = f"//check ISA:=regex(.*{xlen}.*);check ISA:=regex({ext_regex});def TEST_CASE_1=True;"
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if ext_parts_no_I[-1] == 'D':
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ext_parts_no_I = ext_parts_no_I[:-1]
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if ext_parts_no_I[-1] == 'M':
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ext_parts_no_I = ext_parts_no_I[:-1]
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if ext_parts_no_I[-1] == 'F':
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ext_parts_no_I = ext_parts_no_I[:-1]
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if "I" not in ext_parts_no_I and "E" not in ext_parts_no_I:
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ext_parts_no_I = ['I'] + ext_parts_no_I
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# Join single char items with no separator, multi-char items with underscore
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ext_str = ""
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for ext in ext_parts_no_I:
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if len(ext) > 1:
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ext_str += "_"
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ext_str += ext
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march = f"rv{xlen}{ext_str.lower()}"
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march = march.replace("zaamo", "a").replace("zalrsc", "a") # gcc 14 does not accept Zaamo/Zalrsc
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# Replace placeholders
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template = template.replace("@EXTENSION_LIST@", f"{ext_parts_no_I}")
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template = template.replace("@MARCH@", march)
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template = template.replace("@XLEN@", str(xlen))
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template = template.replace("@CONFIG_DEPENDENT@", "false") # TODO: Make this configurable for some tests (e.g. Zimop)
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template = template.replace("sigupd_count", str(signatureWords))
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template = template.replace("ISAEXT", ISAEXT)
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template = template.replace("TestCase", test_case_line)
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template = template.replace("Instruction", test)
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if is_custom:
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# Count SIGUPD macros

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