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Bump addins/cvw-arch-verif from
Bumps [addins/cvw-arch-verif](https://github.com/openhwgroup/cvw-arch-verif) from `c3700b4` to `4fe822a`.
- [Commits](openhwgroup/cvw-arch-verif@c3700b4...4fe822a)
---
updated-dependencies:
- dependency-name: addins/cvw-arch-verif
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>c3700b4 to 4fe822a
1 parent 1f0e247 commit 0c7c5ca
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lines changedSubmodule cvw-arch-verif updated 49 files
- .editorconfig+12
- .gitmodules-3
- Makefile+2-2
- bin/combinetests.py+57-57
- bin/coverreport.py+2-2
- bin/makeselfchecking.py+77-77
- bin/testgen.py+4
- fcov/RISCV_coverage.svh+44
- fcov/coverage/RISCV_coverage_base.svh+64-91
- fcov/coverage/RISCV_coverage_common.svh+739
- fcov/coverage/RISCV_coverage_config.svh+183
- fcov/coverage/RISCV_coverage_csr.svh+933
- fcov/coverage/RISCV_coverage_exceptions.svh+42
- fcov/coverage/RISCV_coverage_hazards.svh+99
- fcov/coverage/RISCV_coverage_pkg.svh+27
- fcov/coverage/RISCV_coverage_rvvi.svh+136
- fcov/coverage/RISCV_decode_pkg.svh+1.5k
- fcov/coverage/RISCV_disassemble_helpers.svh+668
- fcov/coverage/RISCV_instruction_base.svh+469-487
- fcov/coverage/RISCV_trace_data.svh+131-105
- fcov/cvw-arch-verif.f+35
- fcov/cvw_arch_verif.sv+55
- fcov/disassemble.svh+592
- fcov/priv/ExceptionsM_coverage.svh+14-12
- fcov/priv/ExceptionsS_coverage.svh+223
- fcov/priv/ExceptionsS_coverage_init.svh+11
- fcov/priv/ExceptionsU_coverage.svh+3-1
- fcov/priv/ZicsrF_coverage.svh+8-8
- fcov/rvviTrace.sv+149
- riscvISACOV-1
- setup.sh+5
- templates/cp_imm_corners_20bit.txt+5-5
- templates/cp_imm_corners_c_jal.txt+2-2
- templates/cp_imm_corners_clui.txt+4-4
- templates/cp_imm_corners_jal.txt+2-2
- templates/cp_imm_mul.txt+1-1
- templates/cp_imm_mul_4sp.txt+1-1
- templates/cp_imm_mul_8.txt+1-1
- templates/cp_imm_mul_8sp.txt+1-1
- templates/cp_imm_mul_addi16sp.txt+1-1
- templates/cp_imm_mul_addi4spn.txt+1-1
- templates/cp_offset.txt+1-1
- templates/cp_offset_c_jr.txt+1-1
- templates/cp_offset_jalr.txt+1-1
- templates/cp_sc.txt+1-1
- templates/cr_rs1_imm_corners_6bit_n0.txt+17
- templates/sample_CJAL.txt+1-2
- testplans/Zca.csv+5-5
- tests/lockstep/priv/InterruptsM.S-223
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