Merge pull request #1316 from jordancarlin/rv32imc_lockstep

Add rv32IMC Imperas Configuration for Lockstep

Author: davidharrishmc

bin/regression-wally

@@ -42,7 +42,7 @@ testfloatsim = "questa"    # change to Verilator when Issue #707 about testfloat
 standard_tests = [
         ["rv32e", ["arch32e"]],
         ["rv32i", ["arch32i"]],
-        ["rv32imc", ["arch32i", "arch32c", "arch32m", "wally32periph"]],
+        ["rv32imc", ["arch32i", "arch32c", "arch32m"]], # add when issue #1321 is fixed: "wally32periph"
         ["rv32gc", ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt",
                     "arch32i", "arch32priv", "arch32c",  "arch32m", "arch32a_amo", "arch32zifencei", "arch32zicond",
                     "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma",

config/rv32imc/config.vh

@@ -38,7 +38,7 @@ localparam logic IEEE754 = 0;
 localparam logic E_SUPPORTED = 0;
 
 // Integer instruction set extensions
-localparam logic ZIFENCEI_SUPPORTED = 1; // Instruction-Fetch fence
+localparam logic ZIFENCEI_SUPPORTED = 0; // Instruction-Fetch fence
 localparam logic ZICSR_SUPPORTED    = 1; // CSR Instructions
 localparam logic ZICCLSM_SUPPORTED  = 0; // Misaligned loads/stores
 localparam logic ZICOND_SUPPORTED   = 0; // Integer conditional operations
@@ -85,7 +85,7 @@ localparam logic ZFH_SUPPORTED = 0;
 localparam logic ZFA_SUPPORTED = 0;
 
 // privilege modes
-localparam logic S_SUPPORTED = 1; // Supervisor mode
+localparam logic S_SUPPORTED = 0; // Supervisor mode
 localparam logic U_SUPPORTED = 1; // User mode
 
 // Supervisor level extensions

config/rv32imc/coverage.svh

@@ -0,0 +1,30 @@
+// coverage.svh
+// David_Harris@hmc.edu 7 September 2024
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+// This file is needed in the config subdirectory for each config supporting coverage.
+// It defines which extensions are enabled for that config.
+
+// Define XLEN, used in covergroups
+`define XLEN32
+
+// Define relevant addresses
+`define ACCESS_FAULT_ADDRESS 32'h0000
+`define CLINT_BASE 64'h02000000
+
+// Unprivileged extensions
+`define I_COVERAGE
+`define M_COVERAGE
+`define ZCA_COVERAGE
+`define ZICSR_COVERAGE
+
+// Privileged extensions
+`define ZICSRM_COVERAGE
+`define ZICSRU_COVERAGE
+`define EXCEPTIONSM_COVERAGE
+`define EXCEPTIONSU_COVERAGE
+`define EXCEPTIONSZC_COVERAGE
+`define ZICNTRU_COVERAGE
+`define ZICNTRM_COVERAGE
+`define INTERRUPTSU_COVERAGE
+`define INTERRUPTSM_COVERAGE

config/rv32imc/imperas.ic

@@ -0,0 +1,80 @@
+# imperas.ic
+# Initialization file for ImperasDV lock step simulation
+# David_Harris@hmc.edu 15 August 2024
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+#--mpdconsole
+#--gdbconsole
+#--showoverrides
+#--showcommands
+
+# Core settings
+--variant RV32IMC
+--override cpu/priv_version=1.12
+--override cpu/user_version=20191213
+# arch
+--override cpu/mimpid=0x100
+--override cpu/mvendorid=0x602
+--override cpu/marchid=0x24
+--override refRoot/cpu/tvec_align=64
+
+# No Supervisor mode
+--override cpu/sub_Extensions="S"
+
+# Zifencei extension not implemented
+--override cpu/Zifencei=F
+
+# Little endian only
+--override cpu/endianFixed=T
+
+# For code coverage, don't produce pseudoinstructions
+--override no_pseudo_inst=T
+
+# Show "c." with compressed instructions
+--override show_c_prefix=T
+
+# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
+--override cpu/ecode_mask=0x8000000F  # for RV32
+
+# disable CSRs 7a0-7a8
+--override cpu/trigger_num=0
+
+# Reset address
+--override cpu/reset_address=0x80000000
+
+# Wally implementats WFI as NOP
+--override cpu/wfi_is_nop=T
+
+# MISA not writable
+--override cpu/misa_Extensions_mask=0x0
+
+# No PMP
+--override cpu/PMP_registers=0
+--override cpu/PMP_undefined=T
+
+# PMA Settings
+# 'r': read access allowed
+# 'w': write access allowed
+# 'x': execute access allowed
+# 'a': aligned access required
+# 'A': atomic instructions NOT allowed (actually USER1 privilege needed)
+# 'P': push/pop instructions NOT allowed (actually USER2 privilege needed)
+# '1': 1-byte accesses allowed
+# '2': 2-byte accesses allowed
+# '4': 4-byte accesses allowed
+# '8': 8-byte accesses allowed
+# '-', space: ignored (use for input string formatting).
+#
+# SVxx Memory 0x0000000000 0x7FFFFFFFFF
+#
+--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0xFFFFFFFFFFFFFFFFFF -attributes " ---a-- ---- " # All memory inaccessible unless defined otherwise
+--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ---a-- ---- " # INITIAL
+--callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw-aA- 1248 " # CLINT
+--callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw-aA- --4- " # PLIC
+--callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw-aA- 1--- " # UART0
+--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw-aA- --4- " # GPIO
+--callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw-aA- --4- " # SPI
+--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x00807FFFFF -attributes " rwx--- 1248 " # DTIM/IROM
+
+# Store simulator output to logfile
+--output imperas.log

testbench/common/wallyTracer.sv

@@ -220,28 +220,34 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
     // Machine Information Registers and Configuration CSRs
     `CONNECT_CSR(MISA, 12'h301, testbench.dut.core.priv.priv.csr.csrm.MISA_REGW);
     `CONNECT_CSR(MENVCFG, 12'h30A, testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW);
-    `CONNECT_CSR(SENVCFG, 12'h10A, testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW);
     `CONNECT_CSR(MSECCFG, 12'h747, 0); // mseccfg
     `CONNECT_CSR(MVENDORID, 12'hF11, 0); //mvendorid
     `CONNECT_CSR(MARCHID, 12'hF12, 0); // marchid
     `CONNECT_CSR(MIMPID, 12'hF13, {{P.XLEN-12{1'b0}}, 12'h100}); // mimpid
     `CONNECT_CSR(MHARTID, 12'hF14, testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW);
     `CONNECT_CSR(MCONFIGPTR, 12'hF15, 0); //mconfigptr
 
+    // Supervisor Information Registers and Configuration CSRs
+    if (P.S_SUPPORTED) begin
+      `CONNECT_CSR(SENVCFG, 12'h10A, testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW);
+    end
+
     // Sstc CSRs
     if (P.SSTC_SUPPORTED) begin
       `CONNECT_CSR(STIMECMP, 12'h14D, testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0]);
+      if (P.XLEN == 32) begin
+        `CONNECT_CSR(STIMECMPH, 12'h15D, testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32]);
+      end
     end
 
     // Zkr CSRs
     // seed not connected (015)
 
-    // extra CSRs for RV32
+    // extra M mode CSRs for RV32
     if (P.XLEN == 32) begin
       `CONNECT_CSR(MSTATUSH, 12'h310, testbench.dut.core.priv.priv.csr.csrsr.MSTATUSH_REGW);
       `CONNECT_CSR(MENVCFGH, 12'h31A, testbench.dut.core.priv.priv.csr.csrm.MENVCFGH_REGW);
       `CONNECT_CSR(MSECCFGH, 12'h757, 0); // mseccfgh
-      `CONNECT_CSR(STIMECMPH, 12'h15D, testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32]);
     end
   end