Merge pull request #1357 from davidharrishmc/dev

Author: jordancarlin

bin/regression-wally

@@ -42,7 +42,7 @@ testfloatsim = "questa"    # change to Verilator when Issue #707 about testfloat
 standard_tests = [
         ["rv32e", ["arch32e"]],
         ["rv32i", ["arch32i"]],
-        ["rv32imc", ["arch32i", "arch32c", "arch32m"]], # add when issue #1321 is fixed: "wally32periph"
+        ["rv32imc", ["arch32i", "arch32c", "arch32m", "wally32periph"]], 
         ["rv32gc", ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt",
                     "arch32i", "arch32priv", "arch32c",  "arch32m", "arch32a_amo", "arch32zifencei", "arch32zicond",
                     "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma",
@@ -436,18 +436,18 @@ def selectTests(args, sims, coverStr):
         addTests(tests_buildrootbootlockstep, lockstepsim, coverStr, configs) # lockstep with Questa and ImperasDV runs overnight
 
     if args.ccov:  # only run RV64GC tests on Questa in code coverage mode
-        addTestsByDir(f"{archVerifDir}/tests/lockstep/rv64/", "rv64gc", coveragesim, coverStr, configs)
-        addTestsByDir(f"{archVerifDir}/tests/lockstep/priv/rv64/", "rv64gc", coveragesim, coverStr, configs)
+        addTestsByDir(f"{archVerifDir}/tests/rv64/", "rv64gc", coveragesim, coverStr, configs)
+        addTestsByDir(f"{archVerifDir}/tests/priv/rv64/", "rv64gc", coveragesim, coverStr, configs) # doesn't help coverage much dh 4/12/25
         addTestsByDir(WALLY+"/tests/coverage/", "rv64gc", coveragesim, coverStr, configs)
         # Extra tests from riscv-arch-test that should be run as part of the functional coverage suite
         addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/pmp", "rv64gc", coveragesim, coverStr, configs)
         addTestsByDir(f"{WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege", "rv64gc", coveragesim, coverStr, configs)
         # addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/F", "rv64gc", coveragesim, coverStr, configs) # doesn't help fdivsqrt coverage 4/3/2025
     elif args.fcov:  # run tests in lockstep in functional coverage mode
-        addTestsByDir(f"{archVerifDir}/tests/lockstep/rv32/", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)
-        addTestsByDir(f"{archVerifDir}/tests/lockstep/rv64/", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1)
-        addTestsByDir(f"{archVerifDir}/tests/lockstep/priv/rv32/", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)
-        addTestsByDir(f"{archVerifDir}/tests/lockstep/priv/rv64/", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1)
+        addTestsByDir(f"{archVerifDir}/tests/rv32/", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)
+        addTestsByDir(f"{archVerifDir}/tests/rv64/", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1)
+        addTestsByDir(f"{archVerifDir}/tests/priv/rv32/", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)
+        addTestsByDir(f"{archVerifDir}/tests/priv/rv64/", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1)
         # Extra tests from riscv-arch-test that should be run as part of the functional coverage suite
         addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/vm_sv32", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)
         # addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/pmp32", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1) TODO: Add when working in lockstep

examples/exercises/fma16/fma16_testgen.c

@@ -42,16 +42,22 @@ void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add
     char calc[80], flags[80];
     float32_t x32, y32, z32, r32;
     float xf, yf, zf, rf;
+    float16_t x2, z2;
     float16_t smallest;
 
     if (!mul) y.v = 0x3C00; // force y to 1 to avoid multiply
     if (!add) z.v = 0x0000; // force z to 0 to avoid add
-    if (negp) x.v ^= 0x8000; // flip sign of x to negate p
-    if (negz) z.v ^= 0x8000; // flip sign of z to negate z
+
+    // Negated versions of x and z are used in the mulAdd call where necessary
+    x2 = x;
+    z2 = z;
+    if (negp) x2.v ^= 0x8000; // flip sign of x to negate p
+    if (negz) z2.v ^= 0x8000; // flip sign of z to negate z
+
     op = roundingMode << 4 | mul<<3 | add<<2 | negp<<1 | negz;
 //    printf("op = %02x rm %d mul %d add %d negp %d negz %d\n", op, roundingMode, mul, add, negp, negz);
     softfloat_exceptionFlags = 0; // clear exceptions
-    result = f16_mulAdd(x, y, z); // call SoftFloat to compute expected result
+    result = f16_mulAdd(x2, y, z2); // call SoftFloat to compute expected result
 
     // Extract expected flags from SoftFloat
     sprintf(flags, "NV: %d OF: %d UF: %d NX: %d", 

sim/questa/coverage-exclusions-rv64gc.do

@@ -346,6 +346,11 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLi
 coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ${SRC}/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboz"] 
 coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ${SRC}/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboaccess"] 
 
+# IMMU PMP only makes 4-byte accesses
+coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ${SRC}/mmu/pmpchecker.sv "SizeBytesMinus1 = 3'd0"]  -item bs 1
+coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ${SRC}/mmu/pmpchecker.sv "SizeBytesMinus1 = 3'd1"]  -item bs 1
+coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ${SRC}/mmu/pmpchecker.sv "SizeBytesMinus1 = 3'd7"]  -item bs 1
+
 # No irom
 set line [GetLineNum ${SRC}/ifu/ifu.sv "~ITLBMissF & ~CacheableF & ~SelIROM"] 
 coverage exclude -scope /dut/core/ifu -linerange $line-$line -item c 1 -feccondrow 6

src/mmu/mmu.sv

@@ -75,7 +75,13 @@ module mmu import cvw::*;  #(parameter cvw_t P,
   logic                        ReadNoAmoAccessM;         // Read that is not part of atomic operation causes Load faults.  Otherwise StoreAmo faults
   logic [1:0]                  PBMemoryType;             // PBMT field of PTE during TLB hit, or 00 otherwise
   logic                        AtomicMisalignedCausesAccessFaultM; // Misaligned atomics are not handled by hardware even with ZICCLSM, so it throws an access fault instead of misaligned with ZICCLSM
+  logic [1:0]                  EffectivePrivilegeModeW;  // Effective privilege mode accounting for MPRV
 
+
+  // Get Effective Privilege Mode
+  // for DLB, when mstatus.MPRV=1, use mstatus.MPP rather than the current privilege mode
+  assign EffectivePrivilegeModeW = IMMU ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW);
+
   // only instantiate TLB if Virtual Memory is supported
   if (P.VIRTMEM_SUPPORTED) begin:tlb
     logic ReadAccess, WriteAccess;
@@ -86,7 +92,7 @@ module mmu import cvw::*;  #(parameter cvw_t P,
           .SATP_MODE(SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]),
           .SATP_ASID(SATP_REGW[P.ASID_BASE+P.ASID_BITS-1:P.ASID_BASE]),
           .VAdr(VAdr[P.XLEN-1:0]), .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
-          .PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOpM,
+          .EffectivePrivilegeModeW, .ReadAccess, .WriteAccess, .CMOpM,
           .DisableTranslation, .PTE, .PageTypeWriteVal,
           .TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss,
           .Translate, .TLBPageFault, .UpdateDA, .PBMemoryType);
@@ -115,7 +121,7 @@ module mmu import cvw::*;  #(parameter cvw_t P,
     .PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM);
 
   if (P.PMP_ENTRIES > 0) begin : pmp
-    pmpchecker #(P) pmpchecker(.PhysicalAddress, .PrivilegeModeW,
+    pmpchecker #(P) pmpchecker(.PhysicalAddress, .EffectivePrivilegeModeW,
       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
       .ExecuteAccessF, .WriteAccessM, .ReadAccessM, .Size, .CMOpM, 
       .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);

src/mmu/pmpadrdec.sv

@@ -33,6 +33,7 @@
 
 module pmpadrdec import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.PA_BITS-1:0]  PhysicalAddress,
+  input  logic [1:0]            Size,
   input  logic [7:0]            PMPCfg,
   input  logic [P.PA_BITS-3:0]  PMPAdr,
   input  logic                  FirstMatch,
@@ -52,7 +53,7 @@ module pmpadrdec import cvw::*;  #(parameter cvw_t P) (
   logic                         PAltPMPAdr;
   logic [P.PA_BITS-1:0]         CurrentAdrFull;
   logic [1:0]                   AdrMode;
-  logic [P.PA_BITS-1:0]         PMPTop1;
+  logic [P.PA_BITS-1:0]         PMPTop1, PMPTopTOR, PMPTopNaturallyAligned;
 
   assign AdrMode = PMPCfg[4:3];
 
@@ -83,10 +84,12 @@ module pmpadrdec import cvw::*;  #(parameter cvw_t P) (
                  1'b0;
 
   // Report top of region for first matching region
-  assign PMPTop1 = {PMPAdr,2'b00} | NAMask; // top of the pmp region.  All 1s in the lower bits.  Used to check the address doesn't pass the top
+  // PMP should match but fail if the size is too big (8-byte accesses spanning to TOR or NA4 region)
+  assign PMPTopTOR = {PMPAdr-1,  2'b11}; // TOR goes to (pmpaddr << 2) - 1
+  assign PMPTopNaturallyAligned = {PMPAdr,2'b00} | NAMask; // top of the pmp region for NA4 and NAPOT.  All 1s in the lower bits.  Used to check the address doesn't pass the top
+  assign PMPTop1 = (AdrMode == TOR) ? PMPTopTOR : PMPTopNaturallyAligned;
   assign PMPTop = FirstMatch ? PMPTop1 : '0; // AND portion of distributed AND-OR mux (OR portion in pmpchhecker)
 
-  // PMP should match but fail if the size is too big (8-byte accesses spanning to TOR or NA4 region)
   assign L = PMPCfg[7];
   assign X = PMPCfg[2];
   assign W = PMPCfg[1];

src/mmu/pmpchecker.sv

@@ -32,7 +32,7 @@
 
 module pmpchecker import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.PA_BITS-1:0]     PhysicalAddress,  
-  input  logic [1:0]               PrivilegeModeW,
+  input  logic [1:0]               EffectivePrivilegeModeW,
   // ModelSim has a switch -svinputport which controls whether input ports
   // are nets (wires) or vars by default. The default setting of this switch is
   // `relaxed`, which means that signals are nets if and only if they are
@@ -66,6 +66,7 @@ module pmpchecker import cvw::*;  #(parameter cvw_t P) (
   if (P.PMP_ENTRIES > 0) begin: pmp // prevent complaints about array of no elements when PMP_ENTRIES = 0
     pmpadrdec #(P) pmpadrdecs[P.PMP_ENTRIES-1:0](
       .PhysicalAddress, 
+      .Size,
       .PMPCfg(PMPCFG_ARRAY_REGW),
       .PMPAdr(PMPADDR_ARRAY_REGW),
       .FirstMatch,
@@ -97,8 +98,8 @@ module pmpchecker import cvw::*;  #(parameter cvw_t P) (
   assign PhysicalAddressTop = PhysicalAddress + {{P.PA_BITS-3{1'b0}}, SizeBytesMinus1}; // top of the access range
   assign TooBig = PhysicalAddressTop > MatchingPMPTop; // check if the access goes beyond the top of the PMP region
 
-  // Only enforce PMP checking for S and U modes or in Machine mode when L bit is set in selected region
-  assign EnforcePMP = (PrivilegeModeW != P.M_MODE) | MatchingL;
+  // Only enforce PMP checking for effective S and U modes (accounting for mstatus.MPRV) or in Machine mode when L bit is set in selected region
+  assign EnforcePMP = (EffectivePrivilegeModeW != P.M_MODE) | MatchingL;
 
   assign PMPCBOMAccessFault     = EnforcePMP & (|CMOpM[2:0]) & ~MatchingR ; // checking R is sufficient because W implies R in PMP  // exclusion-tag: immu-pmpcbom
   assign PMPCBOZAccessFault     = EnforcePMP & CMOpM[3] & ~MatchingW ;          // exclusion-tag: immu-pmpcboz

src/mmu/tlb/tlb.sv

@@ -60,7 +60,7 @@ module tlb import cvw::*;  #(parameter cvw_t P,
   input  logic [1:0]               STATUS_MPP,
   input  logic                     ENVCFG_PBMTE,     // Page-based memory types enabled
   input  logic                     ENVCFG_ADUE,      // HPTW A/D Update enable
-  input  logic [1:0]               PrivilegeModeW,   // Current privilege level of the processeor
+  input  logic [1:0]               EffectivePrivilegeModeW,   // Current privilege level of the processeor, accounting for mstatus.MPRV
   input  logic                     ReadAccess, 
   input  logic                     WriteAccess,
   input  logic [3:0]               CMOpM,
@@ -110,7 +110,7 @@ module tlb import cvw::*;  #(parameter cvw_t P,
   assign NAPOT4 = (PPN[3:0] == 4'b1000); // 64 KiB contiguous region with pte.napot_bits = 4
 
   tlbcontrol #(P, ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
-    .PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOpM, .DisableTranslation,
+    .EffectivePrivilegeModeW, .ReadAccess, .WriteAccess, .CMOpM, .DisableTranslation,
     .PTEAccessBits, .CAMHit, .Misaligned, .NAPOT4, 
     .TLBMiss, .TLBHit, .TLBPageFault, 
     .UpdateDA, .SV39Mode, .Translate, .PTE_N, .PBMemoryType);

src/mmu/tlb/tlbcontrol.sv

@@ -34,7 +34,7 @@ module tlbcontrol import cvw::*;  #(parameter cvw_t P, ITLB = 0) (
   input  logic [1:0]               STATUS_MPP,
   input  logic                     ENVCFG_PBMTE,       // Page-based memory types enabled
   input  logic                     ENVCFG_ADUE,        // HPTW A/D Update enable
-  input  logic [1:0]               PrivilegeModeW,     // Current privilege level of the processeor
+  input  logic [1:0]               EffectivePrivilegeModeW,   // Current privilege level of the processeor, accounting for mstatus.MPRV
   input  logic                     ReadAccess, WriteAccess,
   input  logic [3:0]               CMOpM,
   input  logic                     DisableTranslation,
@@ -53,8 +53,6 @@ module tlbcontrol import cvw::*;  #(parameter cvw_t P, ITLB = 0) (
 );
 
   // Sections of the page table entry
-  logic [1:0]                     EffectivePrivilegeMode;
-
   logic [1:0]                     PTE_PBMT;
   logic                           PTE_RESERVED, PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R, PTE_V; // Useful PTE Control Bits
   logic                           UpperBitsUnequal;
@@ -66,8 +64,7 @@ module tlbcontrol import cvw::*;  #(parameter cvw_t P, ITLB = 0) (
   logic                           PreUpdateDA, PrePageFault;
 
   // Grab the sv mode from SATP and determine whether translation should occur
-  assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1
-  assign Translate = (SATP_MODE != P.NO_TRANSLATE[P.SVMODE_BITS-1:0]) & (EffectivePrivilegeMode != P.M_MODE) & ~DisableTranslation; 
+  assign Translate = (SATP_MODE != P.NO_TRANSLATE[P.SVMODE_BITS-1:0]) & (EffectivePrivilegeModeW != P.M_MODE) & ~DisableTranslation; 
 
   // Determine whether TLB is being used
   assign TLBAccess = ReadAccess | WriteAccess | (|CMOpM);
@@ -95,7 +92,7 @@ module tlbcontrol import cvw::*;  #(parameter cvw_t P, ITLB = 0) (
   if (ITLB == 1) begin:itlb // Instruction TLB fault checking
     // User mode may only execute user mode pages, and supervisor mode may
     // only execute non-user mode pages.
-    assign ImproperPrivilege = ((PrivilegeModeW == P.U_MODE) & ~PTE_U) | ((PrivilegeModeW == P.S_MODE) & PTE_U);
+    assign ImproperPrivilege = ((EffectivePrivilegeModeW == P.U_MODE) & ~PTE_U) | ((EffectivePrivilegeModeW == P.S_MODE) & PTE_U);
     assign PreUpdateDA = ~PTE_A;
     assign InvalidAccess = ~PTE_X | ReservedRW;
  end else begin:dtlb // Data TLB fault checking
@@ -104,8 +101,8 @@ module tlbcontrol import cvw::*;  #(parameter cvw_t P, ITLB = 0) (
 
     // User mode may only load/store from user mode pages, and supervisor mode
     // may only access user mode pages when STATUS_SUM is low.
-    assign ImproperPrivilege = ((EffectivePrivilegeMode == P.U_MODE) & ~PTE_U) |
-      ((EffectivePrivilegeMode == P.S_MODE) & PTE_U & ~STATUS_SUM);
+    assign ImproperPrivilege = ((EffectivePrivilegeModeW == P.U_MODE) & ~PTE_U) |
+      ((EffectivePrivilegeModeW == P.S_MODE) & PTE_U & ~STATUS_SUM);
     // Check for read error. Reads are invalid when the page is not readable
     // (and executable pages are not readable) or when the page is neither
     // readable nor executable (and executable pages are readable).

testbench/tests.vh

@@ -194,7 +194,6 @@ string arch32pmp[] = '{
   "rv32i_m/pmp32/src/pmp-TOR-X.S"
 };
 
-// Tests commented out pending riscv-arch-test issue #588
 string arch64pmp[] = '{
   `RISCVARCHTEST,
   "rv64i_m/pmp/src/pmp64-CSR-ALL-MODES.S",
@@ -203,10 +202,10 @@ string arch64pmp[] = '{
   "rv64i_m/pmp/src/pmp64-NA4-U.S",
   "rv64i_m/pmp/src/pmp64-NAPOT-M.S",
   "rv64i_m/pmp/src/pmp64-NAPOT-S.S",
-  "rv64i_m/pmp/src/pmp64-NAPOT-U.S"
-  // "rv64i_m/pmp/src/pmp64-TOR-M.S", TODO: Reenable when Wally top of PMP region bug is fixed
-  // "rv64i_m/pmp/src/pmp64-TOR-S.S",
-  // "rv64i_m/pmp/src/pmp64-TOR-U.S"
+  "rv64i_m/pmp/src/pmp64-NAPOT-U.S",
+  "rv64i_m/pmp/src/pmp64-TOR-M.S",
+  "rv64i_m/pmp/src/pmp64-TOR-S.S",
+  "rv64i_m/pmp/src/pmp64-TOR-U.S"
 };
 
 string arch32vm_sv32[] = '{
@@ -253,7 +252,6 @@ string arch64priv[] = '{
   `RISCVARCHTEST,
   "rv64i_m/privilege/src/ebreak.S",
   "rv64i_m/privilege/src/ecall.S",
-  // "rv64i_m/privilege/src/misalign1-jalr-01.S",
   "rv64i_m/privilege/src/misalign2-jalr-01.S",
   "rv64i_m/privilege/src/misalign-beq-01.S",
   "rv64i_m/privilege/src/misalign-bge-01.S",
@@ -262,7 +260,7 @@ string arch64priv[] = '{
   "rv64i_m/privilege/src/misalign-bltu-01.S",
   "rv64i_m/privilege/src/misalign-bne-01.S",
   "rv64i_m/privilege/src/misalign-jal-01.S"
-  // removed because rv64gc supports Zicclsm
+  // commented out for now because rv64gc supports Zicclsm, but Sail does not yet.  Restore when Sail supports Zicclsm.
   /* -----\/----- EXCLUDED -----\/-----
   "rv64i_m/privilege/src/misalign-ld-01.S",
   "rv64i_m/privilege/src/misalign-lh-01.S",
@@ -2014,7 +2012,6 @@ string arch32priv[] = '{
   `RISCVARCHTEST,
   "rv32i_m/privilege/src/ebreak.S",
   "rv32i_m/privilege/src/ecall.S",
-  // "rv32i_m/privilege/src/misalign1-jalr-01.S",
   "rv32i_m/privilege/src/misalign2-jalr-01.S",
   "rv32i_m/privilege/src/misalign-beq-01.S",
   "rv32i_m/privilege/src/misalign-bge-01.S",
@@ -3587,6 +3584,7 @@ string wally32priv[] = '{
   "rv32i_m/privilege/src/WALLY-endianness-01.S",
   "rv32i_m/privilege/src/WALLY-satp-invalid-01.S",
   // These peripherals are here instead of wally32periph because they don't work on rv32imc, which lacks a PMP register to configure
+  "rv32i_m/privilege/src/WALLY-periph-s-01.S",
   "rv32i_m/privilege/src/WALLY-gpio-01.S",
   "rv32i_m/privilege/src/WALLY-clint-01.S",
   "rv32i_m/privilege/src/WALLY-uart-01.S",