FPU synthesis error within the `lzc` module

[unaimillan]

Good afternoon!

I am trying to synthesize the CVW's FPU block (only single block without other parts of the CPU) and getting wierd error by Quartus Prime synthesis.

The error states the following:

It appears on the line 36 of the lzc.sv file.
The module instantiated in the parent module fmalza.sv line 59.

After updating while loop with stricter stop condition everything starts to work. The update looks like the following:
while ((i < WIDTH-1) & ~num[WIDTH-1-i]) i = i+1; // search for leading one

I am not sure about exact reasons causing the error and the correctness of my solution. I was concerned about the error and decided to report it here just in case.

Quartus Prime version: Lite 21.1.1

[Pablotpa]

Hello, I was having the same problem with Jasper Cadence v2024.12. I was doing the synthesis of the whole CPU in this case. My solution was to replace the file by the lzc.sv from the pulp-platform/common_cells repository. I'm also not sure about this fix, so I hope someone can look into it.

Cheers

[davidharrishmc]

This module synthesizes in Design Compiler, but clearly is giving problems in other tools. Use your favorite workaround for a LZC for now, and we will eventually rewrite the module.

[rosethompson]

This also fails with yosys. @infinitymdm has another implementation that works with yosys; however, the implementation is not as compact. @infinitymdm can you post your solution so we can compare.

[infinitymdm]

Here you go! #1396

[infinitymdm]

For clarity, here's my modified version of the file verbatim:

///////////////////////////////////////////
//
// Written: me@KatherineParry.com
// Modified: 01/23/2025 by marcus@infinitymdm.dev
//
// Purpose: Leading Zero Counter
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////

module lzc #(
    parameter WIDTH = 1,
    parameter CBITS = $clog2(WIDTH+1)
) (
  input  logic [WIDTH-1:0]  num,    // number to count the leading zeroes of
  output logic [CBITS-1:0]    ZeroCnt // the number of leading zeroes
);

    // Use a recursive binary tree structure to avoid unsynthesizable loops
    logic [WIDTH/2-1:0] Lnum, Rnum;
    logic [CBITS-2:0]   LCnt, RCnt;

    assign Lnum = num[WIDTH-1-:WIDTH/2];
    assign Rnum = num[WIDTH/2-1-:WIDTH/2];
    generate
        if (WIDTH <= 2) begin
            assign ZeroCnt = (num == 2'b00) ? 2'b10 :
                             (num == 2'b01) ? 2'b01 : 2'b00;
        end else begin
            lzc #(WIDTH/2) l_lcz (Lnum, LCnt);
            lzc #(WIDTH/2) r_lcz (Rnum, RCnt);
            assign ZeroCnt = (~LCnt[CBITS-2]) ? {LCnt[CBITS-2] & RCnt[CBITS-2],           1'b0, LCnt[CBITS-3:0]} :
                                                {LCnt[CBITS-2] & RCnt[CBITS-2], ~RCnt[CBITS-2], RCnt[CBITS-3:0]};
        end
    endgenerate

endmodule

@rosethompson should I reopen #1396? There are certainly other ways to avoid a while loop, but a recursive binary tree was the obvious solution to me in this case.

[stineje]

So sorry for the late reply @unaimillan not sure it's relevant but didn't look closely at this until now. Quartus supports short-circuit logical operators (&&, ||); have you tried changing while ((i < WIDTH) && !num[WIDTH-1-i]). We will investigate further, especially with @infinitymdm addition here. Thanks! Rock on! We hope to get back to you soon.

[rosethompson]

Hi @infinitymdm Yes let's reopen your PR and I think we will go ahead and merge it.

[infinitymdm]

@unaimillan with the latest LZC changes in #1657 synthesis should work with Quartus Prime. Could you test this and see?

[stineje]

@unaimillan These are the Quartus scripts I used to synthesize things for lzc.sv

quartus_lzc.zip