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8345146: [PPC64] Make intrinsic conversions between bit representations of half precision values and floats
Reviewed-by: rrich Backport-of: b42d79eb6a6d497dc63718c2854609bebca4498c
1 parent 4159e88 commit b942b5e

14 files changed

+179
-3
lines changed

‎src/hotspot/cpu/ppc/assembler_ppc.hpp‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -514,13 +514,18 @@ class Assembler : public AbstractAssembler {
514514
LFSU_OPCODE = (49u << OPCODE_SHIFT | 00u << 1),
515515
LFSX_OPCODE = (31u << OPCODE_SHIFT | 535u << 1),
516516

517+
LFIWAX_OPCODE = (31u << OPCODE_SHIFT | 855u << 1),
518+
LFIWZX_OPCODE = (31u << OPCODE_SHIFT | 887u << 1),
519+
517520
STFD_OPCODE = (54u << OPCODE_SHIFT | 00u << 1),
518521
STFDU_OPCODE = (55u << OPCODE_SHIFT | 00u << 1),
519522
STFDX_OPCODE = (31u << OPCODE_SHIFT | 727u << 1),
520523
STFS_OPCODE = (52u << OPCODE_SHIFT | 00u << 1),
521524
STFSU_OPCODE = (53u << OPCODE_SHIFT | 00u << 1),
522525
STFSX_OPCODE = (31u << OPCODE_SHIFT | 663u << 1),
523526

527+
STFIWX_OPCODE = (31u << OPCODE_SHIFT | 983u << 1),
528+
524529
FSQRT_OPCODE = (63u << OPCODE_SHIFT | 22u << 1), // A-FORM
525530
FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM
526531

@@ -563,6 +568,10 @@ class Assembler : public AbstractAssembler {
563568
XVDIVSP_OPCODE = (60u << OPCODE_SHIFT | 88u << 3),
564569
XXBRD_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 23u << 16), // XX2-FORM
565570
XXBRW_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 15u << 16), // XX2-FORM
571+
XVCVHPSP_OPCODE= (60u << OPCODE_SHIFT | 475u << 2 | 24u << 16), // XX2-FORM
572+
XVCVSPHP_OPCODE= (60u << OPCODE_SHIFT | 475u << 2 | 25u << 16), // XX2-FORM
573+
XSCVHPDP_OPCODE= (60u << OPCODE_SHIFT | 347u << 2 | 16u << 16), // XX2-FORM
574+
XSCVDPHP_OPCODE= (60u << OPCODE_SHIFT | 347u << 2 | 17u << 16), // XX2-FORM
566575
XXPERM_OPCODE = (60u << OPCODE_SHIFT | 26u << 3),
567576
XXSEL_OPCODE = (60u << OPCODE_SHIFT | 3u << 4),
568577
XXSPLTIB_OPCODE= (60u << OPCODE_SHIFT | 360u << 1),
@@ -2119,6 +2128,9 @@ class Assembler : public AbstractAssembler {
21192128
inline void lfdu( FloatRegister d, int si16, Register a);
21202129
inline void lfdx( FloatRegister d, Register a, Register b);
21212130

2131+
inline void lfiwax(FloatRegister d, Register a, Register b);
2132+
inline void lfiwzx(FloatRegister d, Register a, Register b);
2133+
21222134
// PPC 1, section 4.6.3 Floating-Point Store Instructions
21232135
inline void stfs( FloatRegister s, int si16, Register a);
21242136
inline void stfsu( FloatRegister s, int si16, Register a);
@@ -2127,6 +2139,8 @@ class Assembler : public AbstractAssembler {
21272139
inline void stfdu( FloatRegister s, int si16, Register a);
21282140
inline void stfdx( FloatRegister s, Register a, Register b);
21292141

2142+
inline void stfiwx(FloatRegister s, Register a, Register b);
2143+
21302144
// PPC 1, section 4.6.4 Floating-Point Move Instructions
21312145
inline void fmr( FloatRegister d, FloatRegister b);
21322146
inline void fmr_( FloatRegister d, FloatRegister b);
@@ -2391,6 +2405,10 @@ class Assembler : public AbstractAssembler {
23912405
inline void xxleqv( VectorSRegister d, VectorSRegister a, VectorSRegister b);
23922406
inline void xxbrd( VectorSRegister d, VectorSRegister b);
23932407
inline void xxbrw( VectorSRegister d, VectorSRegister b);
2408+
inline void xvcvhpsp( VectorSRegister d, VectorSRegister b);
2409+
inline void xvcvsphp( VectorSRegister d, VectorSRegister b);
2410+
inline void xscvhpdp( VectorSRegister d, VectorSRegister b);
2411+
inline void xscvdphp( VectorSRegister d, VectorSRegister b);
23942412
inline void xxland( VectorSRegister d, VectorSRegister a, VectorSRegister b);
23952413
inline void xxsel( VectorSRegister d, VectorSRegister a, VectorSRegister b, VectorSRegister c);
23962414
inline void xxspltib( VectorSRegister d, int ui8);
@@ -2536,10 +2554,13 @@ class Assembler : public AbstractAssembler {
25362554
inline void lfsx( FloatRegister d, Register b);
25372555
inline void lfd( FloatRegister d, int si16);
25382556
inline void lfdx( FloatRegister d, Register b);
2557+
inline void lfiwax(FloatRegister d, Register b);
2558+
inline void lfiwzx(FloatRegister d, Register b);
25392559
inline void stfs( FloatRegister s, int si16);
25402560
inline void stfsx( FloatRegister s, Register b);
25412561
inline void stfd( FloatRegister s, int si16);
25422562
inline void stfdx( FloatRegister s, Register b);
2563+
inline void stfiwx(FloatRegister s, Register b);
25432564
inline void lvebx( VectorRegister d, Register s2);
25442565
inline void lvehx( VectorRegister d, Register s2);
25452566
inline void lvewx( VectorRegister d, Register s2);

‎src/hotspot/cpu/ppc/assembler_ppc.inline.hpp‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -706,6 +706,9 @@ inline void Assembler::lfd( FloatRegister d, int si16, Register a) { emit_int3
706706
inline void Assembler::lfdu(FloatRegister d, int si16, Register a) { emit_int32( LFDU_OPCODE | frt(d) | ra(a) | simm(si16,16)); }
707707
inline void Assembler::lfdx(FloatRegister d, Register a, Register b) { emit_int32( LFDX_OPCODE | frt(d) | ra0mem(a) | rb(b)); }
708708

709+
inline void Assembler::lfiwax(FloatRegister d, Register a, Register b) { emit_int32( LFIWAX_OPCODE | frt(d) | ra0mem(a) |rb(b)); }
710+
inline void Assembler::lfiwzx(FloatRegister d, Register a, Register b) { emit_int32( LFIWZX_OPCODE | frt(d) | ra0mem(a) |rb(b)); }
711+
709712
// PPC 1, section 4.6.3 Floating-Point Store Instructions
710713
// Use ra0mem instead of ra in some instructions below.
711714
inline void Assembler::stfs( FloatRegister s, int si16, Register a) { emit_int32( STFS_OPCODE | frs(s) | ra0mem(a) | simm(si16,16)); }
@@ -715,6 +718,8 @@ inline void Assembler::stfd( FloatRegister s, int si16, Register a) { emit_int3
715718
inline void Assembler::stfdu(FloatRegister s, int si16, Register a) { emit_int32( STFDU_OPCODE | frs(s) | ra(a) | simm(si16,16)); }
716719
inline void Assembler::stfdx(FloatRegister s, Register a, Register b){ emit_int32( STFDX_OPCODE | frs(s) | ra0mem(a) | rb(b)); }
717720

721+
inline void Assembler::stfiwx(FloatRegister s, Register a, Register b) { emit_int32( STFIWX_OPCODE | frs(s) | ra0mem(a) |rb(b)); }
722+
718723
// PPC 1, section 4.6.4 Floating-Point Move Instructions
719724
inline void Assembler::fmr( FloatRegister d, FloatRegister b) { emit_int32( FMR_OPCODE | frt(d) | frb(b) | rc(0)); }
720725
inline void Assembler::fmr_(FloatRegister d, FloatRegister b) { emit_int32( FMR_OPCODE | frt(d) | frb(b) | rc(1)); }
@@ -836,6 +841,10 @@ inline void Assembler::xxlxor( VectorSRegister d, VectorSRegister a, VectorSReg
836841
inline void Assembler::xxleqv( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXLEQV_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
837842
inline void Assembler::xxbrd( VectorSRegister d, VectorSRegister b) { emit_int32( XXBRD_OPCODE | vsrt(d) | vsrb(b) ); }
838843
inline void Assembler::xxbrw( VectorSRegister d, VectorSRegister b) { emit_int32( XXBRW_OPCODE | vsrt(d) | vsrb(b) ); }
844+
inline void Assembler::xvcvhpsp(VectorSRegister d, VectorSRegister b) { emit_int32( XVCVHPSP_OPCODE | vsrt(d) | vsrb(b) ); }
845+
inline void Assembler::xvcvsphp(VectorSRegister d, VectorSRegister b) { emit_int32( XVCVSPHP_OPCODE | vsrt(d) | vsrb(b) ); }
846+
inline void Assembler::xscvhpdp(VectorSRegister d, VectorSRegister b) { emit_int32( XSCVHPDP_OPCODE | vsrt(d) | vsrb(b) ); }
847+
inline void Assembler::xscvdphp(VectorSRegister d, VectorSRegister b) { emit_int32( XSCVDPHP_OPCODE | vsrt(d) | vsrb(b) ); }
839848
inline void Assembler::xvdivsp( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XVDIVSP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
840849
inline void Assembler::xvdivdp( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XVDIVDP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
841850
inline void Assembler::xvabssp( VectorSRegister d, VectorSRegister b) { emit_int32( XVABSSP_OPCODE | vsrt(d) | vsrb(b)); }
@@ -1130,12 +1139,17 @@ inline void Assembler::lfsx(FloatRegister d, Register b) { emit_int32( LFSX_OPCO
11301139
inline void Assembler::lfd( FloatRegister d, int si16) { emit_int32( LFD_OPCODE | frt(d) | simm(si16,16)); }
11311140
inline void Assembler::lfdx(FloatRegister d, Register b) { emit_int32( LFDX_OPCODE | frt(d) | rb(b)); }
11321141

1142+
inline void Assembler::lfiwax(FloatRegister d, Register b) { emit_int32( LFIWAX_OPCODE | frt(d) | rb(b)); }
1143+
inline void Assembler::lfiwzx(FloatRegister d, Register b) { emit_int32( LFIWZX_OPCODE | frt(d) | rb(b)); }
1144+
11331145
// ra0 version
11341146
inline void Assembler::stfs( FloatRegister s, int si16) { emit_int32( STFS_OPCODE | frs(s) | simm(si16, 16)); }
11351147
inline void Assembler::stfsx(FloatRegister s, Register b) { emit_int32( STFSX_OPCODE | frs(s) | rb(b)); }
11361148
inline void Assembler::stfd( FloatRegister s, int si16) { emit_int32( STFD_OPCODE | frs(s) | simm(si16, 16)); }
11371149
inline void Assembler::stfdx(FloatRegister s, Register b) { emit_int32( STFDX_OPCODE | frs(s) | rb(b)); }
11381150

1151+
inline void Assembler::stfiwx(FloatRegister s, Register b) { emit_int32( STFIWX_OPCODE | frs(s) |rb(b)); }
1152+
11391153
// ra0 version
11401154
inline void Assembler::lvebx( VectorRegister d, Register s2) { emit_int32( LVEBX_OPCODE | vrt(d) | rb(s2)); }
11411155
inline void Assembler::lvehx( VectorRegister d, Register s2) { emit_int32( LVEHX_OPCODE | vrt(d) | rb(s2)); }

‎src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1715,7 +1715,7 @@ void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr
17151715
}
17161716

17171717

1718-
void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1718+
void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
17191719
switch (code) {
17201720
case lir_sqrt: {
17211721
__ fsqrt(dest->as_double_reg(), value->as_double_reg());
@@ -1725,6 +1725,14 @@ void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, L
17251725
__ fabs(dest->as_double_reg(), value->as_double_reg());
17261726
break;
17271727
}
1728+
case lir_f2hf: {
1729+
__ f2hf(dest.as_register(), value.as_float_reg(), tmp.as_float_reg());
1730+
break;
1731+
}
1732+
case lir_hf2f: {
1733+
__ hf2f(dest->as_float_reg(), value.as_register());
1734+
break;
1735+
}
17281736
default: {
17291737
ShouldNotReachHere();
17301738
break;

‎src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -690,6 +690,25 @@ void LIRGenerator::do_MathIntrinsic(Intrinsic* x) {
690690
__ abs(value.result(), dst, LIR_OprFact::illegalOpr);
691691
break;
692692
}
693+
case vmIntrinsics::_floatToFloat16: {
694+
assert(x->number_of_arguments() == 1, "wrong type");
695+
LIRItem value(x->argument_at(0), this);
696+
value.load_item();
697+
LIR_Opr dst = rlock_result(x);
698+
LIR_Opr tmp = new_register(T_FLOAT);
699+
// f2hf treats tmp as live_in. Workaround: initialize to some value.
700+
__ move(LIR_OprFact::floatConst(-0.0), tmp); // just to satisfy LinearScan
701+
__ f2hf(value.result(), dst, tmp);
702+
break;
703+
}
704+
case vmIntrinsics::_float16ToFloat: {
705+
assert(x->number_of_arguments() == 1, "wrong type");
706+
LIRItem value(x->argument_at(0), this);
707+
value.load_item();
708+
LIR_Opr dst = rlock_result(x);
709+
__ hf2f(value.result(), dst, LIR_OprFact::illegalOpr);
710+
break;
711+
}
693712
case vmIntrinsics::_dsqrt:
694713
case vmIntrinsics::_dsqrt_strict: {
695714
if (VM_Version::has_fsqrt()) {

‎src/hotspot/cpu/ppc/macroAssembler_ppc.hpp‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -179,6 +179,9 @@ class MacroAssembler: public Assembler {
179179
void inline set_cmp3(Register dst);
180180
// set dst to (treat_unordered_like_less ? -1 : +1)
181181
void inline set_cmpu3(Register dst, bool treat_unordered_like_less);
182+
// Convert between half precision float encoded into a short and a float in a FloatRegister.
183+
void inline f2hf(Register dst, FloatRegister src, FloatRegister tmp);
184+
void inline hf2f(FloatRegister dst, Register src);
182185

183186
inline void pd_patch_instruction(address branch, address target, const char* file, int line);
184187
NOT_PRODUCT(static void pd_print_patched_instruction(address branch);)

‎src/hotspot/cpu/ppc/macroAssembler_ppc.inline.hpp‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -264,6 +264,20 @@ inline void MacroAssembler::set_cmpu3(Register dst, bool treat_unordered_like_le
264264
set_cmp3(dst);
265265
}
266266

267+
inline void MacroAssembler::f2hf(Register dst, FloatRegister src, FloatRegister tmp) {
268+
// Single precision values in FloatRegisters use double precision format on PPC64.
269+
xscvdphp(tmp->to_vsr(), src->to_vsr());
270+
mffprd(dst, tmp);
271+
// Make it a proper short (sign-extended).
272+
extsh(dst, dst);
273+
}
274+
275+
inline void MacroAssembler::hf2f(FloatRegister dst, Register src) {
276+
mtfprd(dst, src);
277+
// Single precision values in FloatRegisters use double precision format on PPC64.
278+
xscvhpdp(dst->to_vsr(), dst->to_vsr());
279+
}
280+
267281
// Convenience bc_far versions
268282
inline void MacroAssembler::blt_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, less), L, optimize); }
269283
inline void MacroAssembler::bgt_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, greater), L, optimize); }

‎src/hotspot/cpu/ppc/ppc.ad‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2125,6 +2125,9 @@ const bool Matcher::match_rule_supported(int opcode) {
21252125
case Op_PopCountI:
21262126
case Op_PopCountL:
21272127
return (UsePopCountInstruction && VM_Version::has_popcntw());
2128+
case Op_ConvF2HF:
2129+
case Op_ConvHF2F:
2130+
return VM_Version::supports_float16();
21282131

21292132
case Op_AddVB:
21302133
case Op_AddVS:
@@ -11345,6 +11348,34 @@ instruct convF2D_reg(regD dst, regF src) %{
1134511348
ins_pipe(pipe_class_default);
1134611349
%}
1134711350

11351+
instruct convF2HF_reg_reg(iRegIdst dst, regF src, regF tmp) %{
11352+
match(Set dst (ConvF2HF src));
11353+
effect(TEMP tmp);
11354+
ins_cost(3 * DEFAULT_COST);
11355+
size(12);
11356+
format %{ "xscvdphp $tmp, $src\t# convert to half precision\n\t"
11357+
"mffprd $dst, $tmp\t# move result from $tmp to $dst\n\t"
11358+
"extsh $dst, $dst\t# make it a proper short"
11359+
%}
11360+
ins_encode %{
11361+
__ f2hf($dst$$Register, $src$$FloatRegister, $tmp$$FloatRegister);
11362+
%}
11363+
ins_pipe(pipe_class_default);
11364+
%}
11365+
11366+
instruct convHF2F_reg_reg(regF dst, iRegIsrc src) %{
11367+
match(Set dst (ConvHF2F src));
11368+
ins_cost(2 * DEFAULT_COST);
11369+
size(8);
11370+
format %{ "mtfprd $dst, $src\t# move source from $src to $dst\n\t"
11371+
"xscvhpdp $dst, $dst\t# convert from half precision"
11372+
%}
11373+
ins_encode %{
11374+
__ hf2f($dst$$FloatRegister, $src$$Register);
11375+
%}
11376+
ins_pipe(pipe_class_default);
11377+
%}
11378+
1134811379
//----------Control Flow Instructions------------------------------------------
1134911380
// Compare Instructions
1135011381

‎src/hotspot/cpu/ppc/stubGenerator_ppc.cpp‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3557,6 +3557,24 @@ class StubGenerator: public StubCodeGenerator {
35573557
return start;
35583558
}
35593559

3560+
address generate_floatToFloat16() {
3561+
__ align(CodeEntryAlignment);
3562+
StubCodeMark mark(this, "StubRoutines", "floatToFloat16");
3563+
address start = __ function_entry();
3564+
__ f2hf(R3_RET, F1_ARG1, F0);
3565+
__ blr();
3566+
return start;
3567+
}
3568+
3569+
address generate_float16ToFloat() {
3570+
__ align(CodeEntryAlignment);
3571+
StubCodeMark mark(this, "StubRoutines", "float16ToFloat");
3572+
address start = __ function_entry();
3573+
__ hf2f(F1_RET, R3_ARG1);
3574+
__ blr();
3575+
return start;
3576+
}
3577+
35603578
address generate_nmethod_entry_barrier() {
35613579
__ align(CodeEntryAlignment);
35623580
StubCodeMark mark(this, "StubRoutines", "nmethod_entry_barrier");
@@ -4755,6 +4773,12 @@ class StubGenerator: public StubCodeGenerator {
47554773
StubRoutines::_crc32c_table_addr = StubRoutines::ppc::generate_crc_constants(REVERSE_CRC32C_POLY);
47564774
StubRoutines::_updateBytesCRC32C = generate_CRC32_updateBytes(true);
47574775
}
4776+
4777+
if (VM_Version::supports_float16()) {
4778+
// For results consistency both intrinsics should be enabled.
4779+
StubRoutines::_hf2f = generate_float16ToFloat();
4780+
StubRoutines::_f2hf = generate_floatToFloat16();
4781+
}
47584782
}
47594783

47604784
void generate_continuation_stubs() {

‎src/hotspot/cpu/ppc/templateInterpreterGenerator_ppc.cpp‎

Lines changed: 38 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1156,6 +1156,44 @@ address TemplateInterpreterGenerator::generate_math_entry(AbstractInterpreter::M
11561156
return entry;
11571157
}
11581158

1159+
address TemplateInterpreterGenerator::generate_Float_floatToFloat16_entry() {
1160+
if (!VM_Version::supports_float16()) return nullptr;
1161+
1162+
address entry = __ pc();
1163+
1164+
__ lfs(F1, Interpreter::stackElementSize, R15_esp);
1165+
__ f2hf(R3_RET, F1, F0);
1166+
1167+
// Restore caller sp for c2i case (from compiled) and for resized sender frame (from interpreted).
1168+
__ resize_frame_absolute(R21_sender_SP, R11_scratch1, R0);
1169+
__ blr();
1170+
1171+
__ flush();
1172+
1173+
return entry;
1174+
}
1175+
1176+
address TemplateInterpreterGenerator::generate_Float_float16ToFloat_entry() {
1177+
if (!VM_Version::supports_float16()) return nullptr;
1178+
1179+
address entry = __ pc();
1180+
1181+
// Note: Could also use:
1182+
//__ li(R3, Interpreter::stackElementSize);
1183+
//__ lfiwax(F1_RET, R15_esp, R3); // short stored as 32 bit integer
1184+
//__ xscvhpdp(F1_RET->to_vsr(), F1_RET->to_vsr());
1185+
__ lwa(R3, Interpreter::stackElementSize, R15_esp);
1186+
__ hf2f(F1_RET, R3);
1187+
1188+
// Restore caller sp for c2i case (from compiled) and for resized sender frame (from interpreted).
1189+
__ resize_frame_absolute(R21_sender_SP, R11_scratch1, R0);
1190+
__ blr();
1191+
1192+
__ flush();
1193+
1194+
return entry;
1195+
}
1196+
11591197
void TemplateInterpreterGenerator::bang_stack_shadow_pages(bool native_call) {
11601198
// Quick & dirty stack overflow checking: bang the stack & handle trap.
11611199
// Note that we do the banging after the frame is setup, since the exception
@@ -1936,8 +1974,6 @@ address TemplateInterpreterGenerator::generate_Float_intBitsToFloat_entry() { re
19361974
address TemplateInterpreterGenerator::generate_Float_floatToRawIntBits_entry() { return nullptr; }
19371975
address TemplateInterpreterGenerator::generate_Double_longBitsToDouble_entry() { return nullptr; }
19381976
address TemplateInterpreterGenerator::generate_Double_doubleToRawLongBits_entry() { return nullptr; }
1939-
address TemplateInterpreterGenerator::generate_Float_float16ToFloat_entry() { return nullptr; }
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address TemplateInterpreterGenerator::generate_Float_floatToFloat16_entry() { return nullptr; }
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// =============================================================================
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// Exceptions

‎src/hotspot/cpu/ppc/vm_version_ppc.hpp‎

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@@ -97,6 +97,8 @@ class VM_Version: public Abstract_VM_Version {
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static bool supports_fast_class_init_checks() { return true; }
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constexpr static bool supports_stack_watermark_barrier() { return true; }
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static bool supports_float16() { return PowerArchitecturePPC64 >= 9; }
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static bool is_determine_features_test_running() { return _is_determine_features_test_running; }
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// CPU instruction support
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static bool has_fsqrt() { return (_features & fsqrt_m) != 0; }

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