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zifeihan
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RealFYang
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8320397: RISC-V: Avoid passing t0 as temp register to MacroAssembler:: cmpxchg_obj_header/cmpxchgptr
Backport-of: 0be0775a762edbefacf4188b4787b039153fe670
1 parent 8e19c8f commit f766080

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5 files changed

+74
-74
lines changed

5 files changed

+74
-74
lines changed

‎src/hotspot/cpu/riscv/gc/x/x_riscv.ad‎

Lines changed: 33 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -52,11 +52,11 @@ static void x_load_barrier_slow_path(MacroAssembler& _masm, const MachNode* node
5252
%}
5353

5454
// Load Pointer
55-
instruct xLoadP(iRegPNoSp dst, memory mem)
55+
instruct xLoadP(iRegPNoSp dst, memory mem, iRegPNoSp tmp)
5656
%{
5757
match(Set dst (LoadP mem));
5858
predicate(UseZGC && !ZGenerational && (n->as_Load()->barrier_data() != 0));
59-
effect(TEMP dst);
59+
effect(TEMP dst, TEMP tmp);
6060

6161
ins_cost(4 * DEFAULT_COST);
6262

@@ -65,17 +65,17 @@ instruct xLoadP(iRegPNoSp dst, memory mem)
6565
ins_encode %{
6666
const Address ref_addr (as_Register($mem$$base), $mem$$disp);
6767
__ ld($dst$$Register, ref_addr);
68-
x_load_barrier(_masm, this, ref_addr, $dst$$Register, t0 /* tmp */, barrier_data());
68+
x_load_barrier(_masm, this, ref_addr, $dst$$Register, $tmp$$Register /* tmp */, barrier_data());
6969
%}
7070

7171
ins_pipe(iload_reg_mem);
7272
%}
7373

74-
instruct xCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
74+
instruct xCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, iRegPNoSp tmp) %{
7575
match(Set res (CompareAndSwapP mem (Binary oldval newval)));
7676
match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
7777
predicate(UseZGC && !ZGenerational && !needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == XLoadBarrierStrong);
78-
effect(KILL cr, TEMP_DEF res);
78+
effect(TEMP_DEF res, TEMP tmp);
7979

8080
ins_cost(2 * VOLATILE_REF_COST);
8181

@@ -86,17 +86,15 @@ instruct xCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newva
8686
Label failed;
8787
guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
8888
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::int64,
89-
Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
90-
true /* result_as_bool */);
91-
__ beqz($res$$Register, failed);
92-
__ mv(t0, $oldval$$Register);
93-
__ bind(failed);
89+
Assembler::relaxed /* acquire */, Assembler::rl /* release */, $tmp$$Register);
90+
__ sub(t0, $tmp$$Register, $oldval$$Register);
91+
__ seqz($res$$Register, t0);
9492
if (barrier_data() != XLoadBarrierElided) {
9593
Label good;
96-
__ ld(t1, Address(xthread, XThreadLocalData::address_bad_mask_offset()), t1 /* tmp */);
97-
__ andr(t1, t1, t0);
98-
__ beqz(t1, good);
99-
x_load_barrier_slow_path(_masm, this, Address($mem$$Register), t0 /* ref */, t1 /* tmp */);
94+
__ ld(t0, Address(xthread, XThreadLocalData::address_bad_mask_offset()));
95+
__ andr(t0, t0, $tmp$$Register);
96+
__ beqz(t0, good);
97+
x_load_barrier_slow_path(_masm, this, Address($mem$$Register), $tmp$$Register /* ref */, $res$$Register /* tmp */);
10098
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::int64,
10199
Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
102100
true /* result_as_bool */);
@@ -107,11 +105,11 @@ instruct xCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newva
107105
ins_pipe(pipe_slow);
108106
%}
109107

110-
instruct xCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
108+
instruct xCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, iRegPNoSp tmp) %{
111109
match(Set res (CompareAndSwapP mem (Binary oldval newval)));
112110
match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
113111
predicate(UseZGC && !ZGenerational && needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == XLoadBarrierStrong));
114-
effect(KILL cr, TEMP_DEF res);
112+
effect(TEMP_DEF res, TEMP tmp);
115113

116114
ins_cost(2 * VOLATILE_REF_COST);
117115

@@ -122,17 +120,15 @@ instruct xCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP ne
122120
Label failed;
123121
guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
124122
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::int64,
125-
Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
126-
true /* result_as_bool */);
127-
__ beqz($res$$Register, failed);
128-
__ mv(t0, $oldval$$Register);
129-
__ bind(failed);
123+
Assembler::aq /* acquire */, Assembler::rl /* release */, $tmp$$Register);
124+
__ sub(t0, $tmp$$Register, $oldval$$Register);
125+
__ seqz($res$$Register, t0);
130126
if (barrier_data() != XLoadBarrierElided) {
131127
Label good;
132-
__ ld(t1, Address(xthread, XThreadLocalData::address_bad_mask_offset()), t1 /* tmp */);
133-
__ andr(t1, t1, t0);
134-
__ beqz(t1, good);
135-
x_load_barrier_slow_path(_masm, this, Address($mem$$Register), t0 /* ref */, t1 /* tmp */);
128+
__ ld(t0, Address(xthread, XThreadLocalData::address_bad_mask_offset()));
129+
__ andr(t0, t0, $tmp$$Register);
130+
__ beqz(t0, good);
131+
x_load_barrier_slow_path(_masm, this, Address($mem$$Register), $tmp$$Register /* ref */, $res$$Register /* tmp */);
136132
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::int64,
137133
Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
138134
true /* result_as_bool */);
@@ -143,10 +139,10 @@ instruct xCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP ne
143139
ins_pipe(pipe_slow);
144140
%}
145141

146-
instruct xCompareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval) %{
142+
instruct xCompareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, iRegPNoSp tmp) %{
147143
match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
148144
predicate(UseZGC && !ZGenerational && !needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == XLoadBarrierStrong);
149-
effect(TEMP_DEF res);
145+
effect(TEMP_DEF res, TEMP tmp);
150146

151147
ins_cost(2 * VOLATILE_REF_COST);
152148

@@ -161,7 +157,7 @@ instruct xCompareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP n
161157
__ ld(t0, Address(xthread, XThreadLocalData::address_bad_mask_offset()));
162158
__ andr(t0, t0, $res$$Register);
163159
__ beqz(t0, good);
164-
x_load_barrier_slow_path(_masm, this, Address($mem$$Register), $res$$Register /* ref */, t0 /* tmp */);
160+
x_load_barrier_slow_path(_masm, this, Address($mem$$Register), $res$$Register /* ref */, $tmp$$Register /* tmp */);
165161
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::int64,
166162
Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register);
167163
__ bind(good);
@@ -171,10 +167,10 @@ instruct xCompareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP n
171167
ins_pipe(pipe_slow);
172168
%}
173169

174-
instruct xCompareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval) %{
170+
instruct xCompareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, iRegPNoSp tmp) %{
175171
match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
176172
predicate(UseZGC && !ZGenerational && needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == XLoadBarrierStrong);
177-
effect(TEMP_DEF res);
173+
effect(TEMP_DEF res, TEMP tmp);
178174

179175
ins_cost(2 * VOLATILE_REF_COST);
180176

@@ -189,7 +185,7 @@ instruct xCompareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iReg
189185
__ ld(t0, Address(xthread, XThreadLocalData::address_bad_mask_offset()));
190186
__ andr(t0, t0, $res$$Register);
191187
__ beqz(t0, good);
192-
x_load_barrier_slow_path(_masm, this, Address($mem$$Register), $res$$Register /* ref */, t0 /* tmp */);
188+
x_load_barrier_slow_path(_masm, this, Address($mem$$Register), $res$$Register /* ref */, $tmp$$Register /* tmp */);
193189
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::int64,
194190
Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register);
195191
__ bind(good);
@@ -199,35 +195,35 @@ instruct xCompareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iReg
199195
ins_pipe(pipe_slow);
200196
%}
201197

202-
instruct xGetAndSetP(indirect mem, iRegP newv, iRegPNoSp prev, rFlagsReg cr) %{
198+
instruct xGetAndSetP(indirect mem, iRegP newv, iRegPNoSp prev, iRegPNoSp tmp) %{
203199
match(Set prev (GetAndSetP mem newv));
204200
predicate(UseZGC && !ZGenerational && !needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() != 0);
205-
effect(TEMP_DEF prev, KILL cr);
201+
effect(TEMP_DEF prev, TEMP tmp);
206202

207203
ins_cost(2 * VOLATILE_REF_COST);
208204

209205
format %{ "atomic_xchg $prev, $newv, [$mem], #@zGetAndSetP" %}
210206

211207
ins_encode %{
212208
__ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
213-
x_load_barrier(_masm, this, Address(noreg, 0), $prev$$Register, t0 /* tmp */, barrier_data());
209+
x_load_barrier(_masm, this, Address(noreg, 0), $prev$$Register, $tmp$$Register /* tmp */, barrier_data());
214210
%}
215211

216212
ins_pipe(pipe_serial);
217213
%}
218214

219-
instruct xGetAndSetPAcq(indirect mem, iRegP newv, iRegPNoSp prev, rFlagsReg cr) %{
215+
instruct xGetAndSetPAcq(indirect mem, iRegP newv, iRegPNoSp prev, iRegPNoSp tmp) %{
220216
match(Set prev (GetAndSetP mem newv));
221217
predicate(UseZGC && !ZGenerational && needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() != 0));
222-
effect(TEMP_DEF prev, KILL cr);
218+
effect(TEMP_DEF prev, TEMP tmp);
223219

224220
ins_cost(VOLATILE_REF_COST);
225221

226222
format %{ "atomic_xchg_acq $prev, $newv, [$mem], #@zGetAndSetPAcq" %}
227223

228224
ins_encode %{
229225
__ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
230-
x_load_barrier(_masm, this, Address(noreg, 0), $prev$$Register, t0 /* tmp */, barrier_data());
226+
x_load_barrier(_masm, this, Address(noreg, 0), $prev$$Register, $tmp$$Register /* tmp */, barrier_data());
231227
%}
232228
ins_pipe(pipe_serial);
233229
%}

‎src/hotspot/cpu/riscv/gc/z/z_riscv.ad‎

Lines changed: 34 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,7 @@ static void z_load_barrier(MacroAssembler& _masm, const MachNode* node, Address
7979

8080
static void z_store_barrier(MacroAssembler& _masm, const MachNode* node, Address ref_addr, Register rnew_zaddress, Register rnew_zpointer, Register tmp, bool is_atomic) {
8181
if (node->barrier_data() == ZBarrierElided) {
82-
z_color(_masm, node, rnew_zpointer, rnew_zaddress, t0);
82+
z_color(_masm, node, rnew_zpointer, rnew_zaddress, tmp);
8383
} else {
8484
bool is_native = (node->barrier_data() & ZBarrierNative) != 0;
8585
ZStoreBarrierStubC2* const stub = ZStoreBarrierStubC2::create(node, ref_addr, rnew_zaddress, rnew_zpointer, is_native, is_atomic);
@@ -90,11 +90,11 @@ static void z_store_barrier(MacroAssembler& _masm, const MachNode* node, Address
9090
%}
9191

9292
// Load Pointer
93-
instruct zLoadP(iRegPNoSp dst, memory mem)
93+
instruct zLoadP(iRegPNoSp dst, memory mem, iRegPNoSp tmp)
9494
%{
9595
match(Set dst (LoadP mem));
9696
predicate(UseZGC && ZGenerational && n->as_Load()->barrier_data() != 0);
97-
effect(TEMP dst);
97+
effect(TEMP dst, TEMP tmp);
9898

9999
ins_cost(4 * DEFAULT_COST);
100100

@@ -103,34 +103,35 @@ instruct zLoadP(iRegPNoSp dst, memory mem)
103103
ins_encode %{
104104
const Address ref_addr(as_Register($mem$$base), $mem$$disp);
105105
__ ld($dst$$Register, ref_addr);
106-
z_load_barrier(_masm, this, ref_addr, $dst$$Register, t0);
106+
z_load_barrier(_masm, this, ref_addr, $dst$$Register, $tmp$$Register);
107107
%}
108108

109109
ins_pipe(iload_reg_mem);
110110
%}
111111

112112
// Store Pointer
113-
instruct zStoreP(memory mem, iRegP src, iRegPNoSp tmp, rFlagsReg cr)
113+
instruct zStoreP(memory mem, iRegP src, iRegPNoSp tmp1, iRegPNoSp tmp2)
114114
%{
115115
predicate(UseZGC && ZGenerational && n->as_Store()->barrier_data() != 0);
116116
match(Set mem (StoreP mem src));
117-
effect(TEMP tmp, KILL cr);
117+
effect(TEMP tmp1, TEMP tmp2);
118118

119119
ins_cost(125); // XXX
120120
format %{ "sd $mem, $src\t# ptr" %}
121121
ins_encode %{
122122
const Address ref_addr(as_Register($mem$$base), $mem$$disp);
123-
z_store_barrier(_masm, this, ref_addr, $src$$Register, $tmp$$Register, t1, false /* is_atomic */);
124-
__ sd($tmp$$Register, ref_addr);
123+
z_store_barrier(_masm, this, ref_addr, $src$$Register, $tmp1$$Register, $tmp2$$Register, false /* is_atomic */);
124+
__ sd($tmp1$$Register, ref_addr);
125125
%}
126126
ins_pipe(pipe_serial);
127127
%}
128128

129-
instruct zCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, iRegPNoSp oldval_tmp, iRegPNoSp newval_tmp, rFlagsReg cr) %{
129+
instruct zCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval,
130+
iRegPNoSp oldval_tmp, iRegPNoSp newval_tmp, iRegPNoSp tmp1) %{
130131
match(Set res (CompareAndSwapP mem (Binary oldval newval)));
131132
match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
132133
predicate(UseZGC && ZGenerational && !needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() != 0);
133-
effect(TEMP oldval_tmp, TEMP newval_tmp, KILL cr, TEMP_DEF res);
134+
effect(TEMP oldval_tmp, TEMP newval_tmp, TEMP tmp1, TEMP_DEF res);
134135

135136
ins_cost(2 * VOLATILE_REF_COST);
136137

@@ -140,19 +141,20 @@ instruct zCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newva
140141
ins_encode %{
141142
guarantee($mem$$disp == 0, "impossible encoding");
142143
Address ref_addr($mem$$Register);
143-
z_color(_masm, this, $oldval_tmp$$Register, $oldval$$Register, t0);
144-
z_store_barrier(_masm, this, ref_addr, $newval$$Register, $newval_tmp$$Register, t1, true /* is_atomic */);
144+
z_color(_masm, this, $oldval_tmp$$Register, $oldval$$Register, $tmp1$$Register);
145+
z_store_barrier(_masm, this, ref_addr, $newval$$Register, $newval_tmp$$Register, $tmp1$$Register, true /* is_atomic */);
145146
__ cmpxchg($mem$$Register, $oldval_tmp$$Register, $newval_tmp$$Register, Assembler::int64, Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register, true /* result_as_bool */);
146147
%}
147148

148149
ins_pipe(pipe_slow);
149150
%}
150151

151-
instruct zCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, iRegPNoSp oldval_tmp, iRegPNoSp newval_tmp, rFlagsReg cr) %{
152+
instruct zCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval,
153+
iRegPNoSp oldval_tmp, iRegPNoSp newval_tmp, iRegPNoSp tmp1) %{
152154
match(Set res (CompareAndSwapP mem (Binary oldval newval)));
153155
match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
154156
predicate(UseZGC && ZGenerational && needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() != 0);
155-
effect(TEMP oldval_tmp, TEMP newval_tmp, KILL cr, TEMP_DEF res);
157+
effect(TEMP oldval_tmp, TEMP newval_tmp, TEMP tmp1, TEMP_DEF res);
156158

157159
ins_cost(2 * VOLATILE_REF_COST);
158160

@@ -162,18 +164,19 @@ instruct zCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP ne
162164
ins_encode %{
163165
guarantee($mem$$disp == 0, "impossible encoding");
164166
Address ref_addr($mem$$Register);
165-
z_color(_masm, this, $oldval_tmp$$Register, $oldval$$Register, t0);
166-
z_store_barrier(_masm, this, ref_addr, $newval$$Register, $newval_tmp$$Register, t1, true /* is_atomic */);
167+
z_color(_masm, this, $oldval_tmp$$Register, $oldval$$Register, $tmp1$$Register);
168+
z_store_barrier(_masm, this, ref_addr, $newval$$Register, $newval_tmp$$Register, $tmp1$$Register, true /* is_atomic */);
167169
__ cmpxchg($mem$$Register, $oldval_tmp$$Register, $newval_tmp$$Register, Assembler::int64, Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register, true /* result_as_bool */);
168170
%}
169171

170172
ins_pipe(pipe_slow);
171173
%}
172174

173-
instruct zCompareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, iRegPNoSp oldval_tmp, iRegPNoSp newval_tmp, rFlagsReg cr) %{
175+
instruct zCompareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval,
176+
iRegPNoSp oldval_tmp, iRegPNoSp newval_tmp, iRegPNoSp tmp1) %{
174177
match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
175178
predicate(UseZGC && ZGenerational && !needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() != 0);
176-
effect(TEMP oldval_tmp, TEMP newval_tmp, KILL cr, TEMP_DEF res);
179+
effect(TEMP oldval_tmp, TEMP newval_tmp, TEMP tmp1, TEMP_DEF res);
177180

178181
ins_cost(2 * VOLATILE_REF_COST);
179182

@@ -182,19 +185,20 @@ instruct zCompareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP n
182185
ins_encode %{
183186
guarantee($mem$$disp == 0, "impossible encoding");
184187
Address ref_addr($mem$$Register);
185-
z_color(_masm, this, $oldval_tmp$$Register, $oldval$$Register, t0);
186-
z_store_barrier(_masm, this, ref_addr, $newval$$Register, $newval_tmp$$Register, t1, true /* is_atomic */);
188+
z_color(_masm, this, $oldval_tmp$$Register, $oldval$$Register, $tmp1$$Register);
189+
z_store_barrier(_masm, this, ref_addr, $newval$$Register, $newval_tmp$$Register, $tmp1$$Register, true /* is_atomic */);
187190
__ cmpxchg($mem$$Register, $oldval_tmp$$Register, $newval_tmp$$Register, Assembler::int64, Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register);
188191
z_uncolor(_masm, this, $res$$Register);
189192
%}
190193

191194
ins_pipe(pipe_slow);
192195
%}
193196

194-
instruct zCompareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, iRegPNoSp oldval_tmp, iRegPNoSp newval_tmp, rFlagsReg cr) %{
197+
instruct zCompareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval,
198+
iRegPNoSp oldval_tmp, iRegPNoSp newval_tmp, iRegPNoSp tmp1) %{
195199
match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
196200
predicate(UseZGC && ZGenerational && needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() != 0);
197-
effect(TEMP oldval_tmp, TEMP newval_tmp, KILL cr, TEMP_DEF res);
201+
effect(TEMP oldval_tmp, TEMP newval_tmp, TEMP tmp1, TEMP_DEF res);
198202

199203
ins_cost(2 * VOLATILE_REF_COST);
200204

@@ -203,44 +207,44 @@ instruct zCompareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iReg
203207
ins_encode %{
204208
guarantee($mem$$disp == 0, "impossible encoding");
205209
Address ref_addr($mem$$Register);
206-
z_color(_masm, this, $oldval_tmp$$Register, $oldval$$Register, t0);
207-
z_store_barrier(_masm, this, ref_addr, $newval$$Register, $newval_tmp$$Register, t1, true /* is_atomic */);
210+
z_color(_masm, this, $oldval_tmp$$Register, $oldval$$Register, $tmp1$$Register);
211+
z_store_barrier(_masm, this, ref_addr, $newval$$Register, $newval_tmp$$Register, $tmp1$$Register, true /* is_atomic */);
208212
__ cmpxchg($mem$$Register, $oldval_tmp$$Register, $newval_tmp$$Register, Assembler::int64, Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register);
209213
z_uncolor(_masm, this, $res$$Register);
210214
%}
211215

212216
ins_pipe(pipe_slow);
213217
%}
214218

215-
instruct zGetAndSetP(indirect mem, iRegP newv, iRegPNoSp prev, rFlagsReg cr) %{
219+
instruct zGetAndSetP(indirect mem, iRegP newv, iRegPNoSp prev, iRegPNoSp tmp) %{
216220
match(Set prev (GetAndSetP mem newv));
217221
predicate(UseZGC && ZGenerational && !needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() != 0);
218-
effect(TEMP_DEF prev, KILL cr);
222+
effect(TEMP_DEF prev, TEMP tmp);
219223

220224
ins_cost(2 * VOLATILE_REF_COST);
221225

222226
format %{ "atomic_xchg $prev, $newv, [$mem], #@zGetAndSetP" %}
223227

224228
ins_encode %{
225-
z_store_barrier(_masm, this, Address($mem$$Register), $newv$$Register, $prev$$Register, t1, true /* is_atomic */);
229+
z_store_barrier(_masm, this, Address($mem$$Register), $newv$$Register, $prev$$Register, $tmp$$Register, true /* is_atomic */);
226230
__ atomic_xchg($prev$$Register, $prev$$Register, $mem$$Register);
227231
z_uncolor(_masm, this, $prev$$Register);
228232
%}
229233

230234
ins_pipe(pipe_serial);
231235
%}
232236

233-
instruct zGetAndSetPAcq(indirect mem, iRegP newv, iRegPNoSp prev, rFlagsReg cr) %{
237+
instruct zGetAndSetPAcq(indirect mem, iRegP newv, iRegPNoSp prev, iRegPNoSp tmp) %{
234238
match(Set prev (GetAndSetP mem newv));
235239
predicate(UseZGC && ZGenerational && needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() != 0);
236-
effect(TEMP_DEF prev, KILL cr);
240+
effect(TEMP_DEF prev, TEMP tmp);
237241

238242
ins_cost(2 * VOLATILE_REF_COST);
239243

240244
format %{ "atomic_xchg_acq $prev, $newv, [$mem], #@zGetAndSetPAcq" %}
241245

242246
ins_encode %{
243-
z_store_barrier(_masm, this, Address($mem$$Register), $newv$$Register, $prev$$Register, t1, true /* is_atomic */);
247+
z_store_barrier(_masm, this, Address($mem$$Register), $newv$$Register, $prev$$Register, $tmp$$Register, true /* is_atomic */);
244248
__ atomic_xchgal($prev$$Register, $prev$$Register, $mem$$Register);
245249
z_uncolor(_masm, this, $prev$$Register);
246250
%}

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