Polish comments: remove the 'RVC:' prefix

Author: zhengxiaolinX

src/hotspot/cpu/riscv/assembler_riscv.hpp

@@ -2045,7 +2045,7 @@ enum Nf {
   void set_in_compressible_region(bool b) { _in_compressible_region = b; }
 public:
 
-// RVC: a compressible region
+  // a compressible region
   class CompressibleRegion : public StackObj {
   protected:
     Assembler *_masm;
@@ -2061,7 +2061,7 @@ enum Nf {
     }
   };
 
-  // RVC: patch a 16-bit instruction.
+  // patch a 16-bit instruction.
   static void c_patch(address a, unsigned msb, unsigned lsb, uint16_t val) {
     assert_cond(a != NULL);
     assert_cond(msb >= lsb && msb <= 15);
@@ -2080,22 +2080,22 @@ enum Nf {
     c_patch(a, bit, bit, val);
   }
 
-  // RVC: patch a 16-bit instruction with a general purpose register ranging [0, 31] (5 bits)
+  // patch a 16-bit instruction with a general purpose register ranging [0, 31] (5 bits)
   static void c_patch_reg(address a, unsigned lsb, Register reg) {
     c_patch(a, lsb + 4, lsb, reg->encoding_nocheck());
   }
 
-  // RVC: patch a 16-bit instruction with a general purpose register ranging [8, 15] (3 bits)
+  // patch a 16-bit instruction with a general purpose register ranging [8, 15] (3 bits)
   static void c_patch_compressed_reg(address a, unsigned lsb, Register reg) {
     c_patch(a, lsb + 2, lsb, reg->compressed_encoding_nocheck());
   }
 
-  // RVC: patch a 16-bit instruction with a float register ranging [0, 31] (5 bits)
+  // patch a 16-bit instruction with a float register ranging [0, 31] (5 bits)
   static void c_patch_reg(address a, unsigned lsb, FloatRegister reg) {
     c_patch(a, lsb + 4, lsb, reg->encoding_nocheck());
   }
 
-  // RVC: patch a 16-bit instruction with a float register ranging [8, 15] (3 bits)
+  // patch a 16-bit instruction with a float register ranging [8, 15] (3 bits)
   static void c_patch_compressed_reg(address a, unsigned lsb, FloatRegister reg) {
     c_patch(a, lsb + 2, lsb, reg->compressed_encoding_nocheck());
   }

src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp

@@ -1323,7 +1323,7 @@ void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Op
 }
 
 void LIR_Assembler::align_call(LIR_Code code) {
-  // RVC: With RVC a call may get 2-byte aligned.
+  // With RVC a call may get 2-byte aligned.
   //   the address of jal itself (which will be patched later) should not span the cache line.
   //   See CallStaticJavaDirectNode::compute_padding() for more info.
   __ align(4);

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp

@@ -2934,7 +2934,7 @@ address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
 
   // make sure 4 byte aligned here, so that the destination address would be
   // 8 byte aligned after 3 intructions
-  // RVC: when we reach here we may get a 2-byte alignment so need to align it
+  // when we reach here we may get a 2-byte alignment so need to align it
   align(wordSize, NativeCallTrampolineStub::data_offset);
 
   relocate(trampoline_stub_Relocation::spec(code()->insts()->start() +

src/hotspot/cpu/riscv/register_riscv.hpp

@@ -60,7 +60,7 @@ class RegisterImpl: public AbstractRegisterImpl {
     number_of_byte_registers = 32,
     max_slots_per_register   = 2,
 
-    // RVC: integer registers in the range of [x8~x15] correspond to RVC. Please see Table 16.2 in spec.
+    // integer registers in the range of [x8~x15] correspond to RVC. Please see Table 16.2 in spec.
     compressed_register_base = 8,
     compressed_register_top  = 15,
   };
@@ -140,7 +140,7 @@ class FloatRegisterImpl: public AbstractRegisterImpl {
     number_of_registers     = 32,
     max_slots_per_register  = 2,
 
-    // RVC: float registers in the range of [f8~f15] correspond to RVC. Please see Table 16.2 in spec.
+    // float registers in the range of [f8~f15] correspond to RVC. Please see Table 16.2 in spec.
     compressed_register_base = 8,
     compressed_register_top  = 15,
   };

src/hotspot/cpu/riscv/riscv.ad

@@ -1190,7 +1190,7 @@ int MachCallNativeNode::ret_addr_offset() {
   return -1;
 }
 
-// RVC: With RVC a call may get 2-byte aligned.
+// With RVC a call may get 2-byte aligned.
 //   The offset encoding in jal ranges bits [12, 31] could span the cache line.
 //   Patching this unaligned address will make the write operation not atomic.
 //   Other threads may be running the same piece of code at full speed, causing concurrency issues.
@@ -1201,7 +1201,7 @@ int CallStaticJavaDirectNode::compute_padding(int current_offset) const
   return align_up(current_offset, alignment_required()) - current_offset;
 }
 
-// RVC: See CallStaticJavaDirectNode::compute_padding() for more info.
+// Please see CallStaticJavaDirectNode::compute_padding() for more info.
 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
 {
   // skip the movptr in MacroAssembler::ic_call():
@@ -1243,7 +1243,7 @@ uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
 
   void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
     C2_MacroAssembler _masm(&cbuf);
-    Assembler::CompressibleRegion cr(&_masm); // RVC: nops shall be 2-byte under RVC for alignment purposes.
+    Assembler::CompressibleRegion cr(&_masm); // nops shall be 2-byte under RVC for alignment purposes.
     for (int i = 0; i < _count; i++) {
       __ nop();
     }