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zhengxiaolinXzhengxiaolinX
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Rename misc functions and change the positions of some comments
1 parent 30020fb commit 1904866

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2 files changed

+48
-47
lines changed

2 files changed

+48
-47
lines changed

‎src/hotspot/cpu/riscv/assembler_riscv.hpp‎

Lines changed: 47 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -2101,15 +2101,15 @@ enum Nf {
21012101
class CompressibleRegion : public StackObj {
21022102
protected:
21032103
Assembler *_masm;
2104-
bool _prev_in_compressible_region;
2104+
bool _saved_in_compressible_region;
21052105
public:
21062106
CompressibleRegion(Assembler *_masm)
21072107
: _masm(_masm)
2108-
, _prev_in_compressible_region(_masm->in_compressible_region()) {
2108+
, _saved_in_compressible_region(_masm->in_compressible_region()) {
21092109
_masm->set_in_compressible_region(true);
21102110
}
21112111
~CompressibleRegion() {
2112-
_masm->set_in_compressible_region(_prev_in_compressible_region);
2112+
_masm->set_in_compressible_region(_saved_in_compressible_region);
21132113
}
21142114
};
21152115

@@ -2596,10 +2596,10 @@ enum Nf {
25962596
// --------------------------
25972597
// Register instructions
25982598
// --------------------------
2599-
// add -> c.add
26002599
#define INSN(NAME) \
26012600
void NAME(Register Rd, Register Rs1, Register Rs2) { \
2602-
if (check_rvc()) { \
2601+
/* add -> c.add */ \
2602+
if (do_compress()) { \
26032603
Register src = noreg; \
26042604
if (Rs1 != x0 && Rs2 != x0 && ((src = Rs1, Rs2 == Rd) || (src = Rs2, Rs1 == Rd))) { \
26052605
c_add(Rd, src); \
@@ -2614,10 +2614,10 @@ enum Nf {
26142614
#undef INSN
26152615

26162616
// --------------------------
2617-
// sub/subw -> c.sub/c.subw
26182617
#define INSN(NAME, C_NAME, NORMAL_NAME) \
26192618
void NAME(Register Rd, Register Rs1, Register Rs2) { \
2620-
if (check_rvc() && \
2619+
/* sub/subw -> c.sub/c.subw */ \
2620+
if (do_compress() && \
26212621
(Rd == Rs1 && Rd->is_compressed_valid() && Rs2->is_compressed_valid())) { \
26222622
C_NAME(Rd, Rs2); \
26232623
return; \
@@ -2631,10 +2631,10 @@ enum Nf {
26312631
#undef INSN
26322632

26332633
// --------------------------
2634-
// xor/or/and/addw -> c.xor/c.or/c.and/c.addw
26352634
#define INSN(NAME, C_NAME, NORMAL_NAME) \
26362635
void NAME(Register Rd, Register Rs1, Register Rs2) { \
2637-
if (check_rvc()) { \
2636+
/* and/or/xor/addw -> c.and/c.or/c.xor/c.addw */ \
2637+
if (do_compress()) { \
26382638
Register src = noreg; \
26392639
if (Rs1->is_compressed_valid() && Rs2->is_compressed_valid() && \
26402640
((src = Rs1, Rs2 == Rd) || (src = Rs2, Rs1 == Rd))) { \
@@ -2654,7 +2654,7 @@ enum Nf {
26542654

26552655
private:
26562656
// some helper functions
2657-
bool check_rvc() const {
2657+
bool do_compress() const {
26582658
return UseRVC && in_compressible_region();
26592659
}
26602660

@@ -2700,10 +2700,10 @@ enum Nf {
27002700
// --------------------------
27012701
// Load/store register
27022702
// --------------------------
2703-
// lw -> c.lwsp/c.lw
27042703
#define INSN(NAME) \
27052704
void NAME(Register Rd, Register Rs, const int32_t offset) { \
2706-
if (check_rvc()) { \
2705+
/* lw -> c.lwsp/c.lw */ \
2706+
if (do_compress()) { \
27072707
if (is_c_lwswsp(Rs, Rd, offset, true)) { \
27082708
c_lwsp(Rd, offset); \
27092709
return; \
@@ -2720,10 +2720,10 @@ enum Nf {
27202720
#undef INSN
27212721

27222722
// --------------------------
2723-
// ld -> c.ldsp/c.ld
27242723
#define INSN(NAME) \
27252724
void NAME(Register Rd, Register Rs, const int32_t offset) { \
2726-
if (check_rvc()) { \
2725+
/* ld -> c.ldsp/c.ld */ \
2726+
if (do_compress()) { \
27272727
if (is_c_ldsdsp(Rs, Rd, offset, true)) { \
27282728
c_ldsp(Rd, offset); \
27292729
return; \
@@ -2740,10 +2740,10 @@ enum Nf {
27402740
#undef INSN
27412741

27422742
// --------------------------
2743-
// fld -> c.fldsp/c.fld
27442743
#define INSN(NAME) \
27452744
void NAME(FloatRegister Rd, Register Rs, const int32_t offset) { \
2746-
if (check_rvc()) { \
2745+
/* fld -> c.fldsp/c.fld */ \
2746+
if (do_compress()) { \
27472747
if (is_c_fldsdsp(Rs, offset)) { \
27482748
c_fldsp(Rd, offset); \
27492749
return; \
@@ -2760,10 +2760,10 @@ enum Nf {
27602760
#undef INSN
27612761

27622762
// --------------------------
2763-
// sd -> c.sdsp/c.sd
27642763
#define INSN(NAME) \
27652764
void NAME(Register Rd, Register Rs, const int32_t offset) { \
2766-
if (check_rvc()) { \
2765+
/* sd -> c.sdsp/c.sd */ \
2766+
if (do_compress()) { \
27672767
if (is_c_ldsdsp(Rs, Rd, offset, false)) { \
27682768
c_sdsp(Rd, offset); \
27692769
return; \
@@ -2780,10 +2780,10 @@ enum Nf {
27802780
#undef INSN
27812781

27822782
// --------------------------
2783-
// sw -> c.swsp/c.sw
27842783
#define INSN(NAME) \
27852784
void NAME(Register Rd, Register Rs, const int32_t offset) { \
2786-
if (check_rvc()) { \
2785+
/* sw -> c.swsp/c.sw */ \
2786+
if (do_compress()) { \
27872787
if (is_c_lwswsp(Rs, Rd, offset, false)) { \
27882788
c_swsp(Rd, offset); \
27892789
return; \
@@ -2800,10 +2800,10 @@ enum Nf {
28002800
#undef INSN
28012801

28022802
// --------------------------
2803-
// fsd -> c.fsdsp/c.fsd
28042803
#define INSN(NAME) \
28052804
void NAME(FloatRegister Rd, Register Rs, const int32_t offset) { \
2806-
if (check_rvc()) { \
2805+
/* fsd -> c.fsdsp/c.fsd */ \
2806+
if (do_compress()) { \
28072807
if (is_c_fldsdsp(Rs, offset)) { \
28082808
c_fsdsp(Rd, offset); \
28092809
return; \
@@ -2822,11 +2822,10 @@ enum Nf {
28222822
// --------------------------
28232823
// Conditional branch instructions
28242824
// --------------------------
2825-
// beq/bne -> c.beqz/c.bnez
2826-
28272825
#define INSN(NAME, C_NAME, NORMAL_NAME) \
28282826
void NAME(Register Rs1, Register Rs2, const int64_t offset) { \
2829-
if (check_rvc() && \
2827+
/* beq/bne -> c.beqz/c.bnez */ \
2828+
if (do_compress() && \
28302829
(offset != 0 && Rs2 == x0 && Rs1->is_compressed_valid() && \
28312830
is_imm_in_range(offset, 8, 1))) { \
28322831
C_NAME(Rs1, offset); \
@@ -2843,10 +2842,10 @@ enum Nf {
28432842
// --------------------------
28442843
// Unconditional branch instructions
28452844
// --------------------------
2846-
// jal -> c.j
28472845
#define INSN(NAME) \
28482846
void NAME(Register Rd, const int32_t offset) { \
2849-
if (check_rvc() && offset != 0 && Rd == x0 && is_imm_in_range(offset, 11, 1)) { \
2847+
/* jal -> c.j */ \
2848+
if (do_compress() && offset != 0 && Rd == x0 && is_imm_in_range(offset, 11, 1)) { \
28502849
c_j(offset); \
28512850
return; \
28522851
} \
@@ -2858,10 +2857,10 @@ enum Nf {
28582857
#undef INSN
28592858

28602859
// --------------------------
2861-
// jalr -> c.jr/c.jalr
28622860
#define INSN(NAME) \
28632861
void NAME(Register Rd, Register Rs, const int32_t offset) { \
2864-
if (check_rvc() && (offset == 0 && Rs != x0)) { \
2862+
/* jalr -> c.jr/c.jalr */ \
2863+
if (do_compress() && (offset == 0 && Rs != x0)) { \
28652864
if (Rd == x1) { \
28662865
c_jalr(Rs); \
28672866
return; \
@@ -2880,10 +2879,10 @@ enum Nf {
28802879
// --------------------------
28812880
// Miscellaneous Instructions
28822881
// --------------------------
2883-
// ebreak -> c.ebreak
28842882
#define INSN(NAME) \
28852883
void NAME() { \
2886-
if (check_rvc()) { \
2884+
/* ebreak -> c.ebreak */ \
2885+
if (do_compress()) { \
28872886
c_ebreak(); \
28882887
return; \
28892888
} \
@@ -2897,10 +2896,10 @@ enum Nf {
28972896
// --------------------------
28982897
// Immediate Instructions
28992898
// --------------------------
2900-
// li -> c.li
29012899
#define INSN(NAME) \
29022900
void NAME(Register Rd, int64_t imm) { \
2903-
if (check_rvc() && (is_imm_in_range(imm, 6, 0) && Rd != x0)) { \
2901+
/* li -> c.li */ \
2902+
if (do_compress() && (is_imm_in_range(imm, 6, 0) && Rd != x0)) { \
29042903
c_li(Rd, imm); \
29052904
return; \
29062905
} \
@@ -2911,10 +2910,11 @@ enum Nf {
29112910

29122911
#undef INSN
29132912

2914-
// addi -> c.addi/c.nop/c.mv/c.addi16sp/c.addi4spn.
2913+
// --------------------------
29152914
#define INSN(NAME) \
29162915
void NAME(Register Rd, Register Rs1, int32_t imm) { \
2917-
if (check_rvc()) { \
2916+
/* addi -> c.addi/c.nop/c.mv/c.addi16sp/c.addi4spn */ \
2917+
if (do_compress()) { \
29182918
if (Rd == Rs1 && is_imm_in_range(imm, 6, 0)) { \
29192919
c_addi(Rd, imm); \
29202920
return; \
@@ -2939,10 +2939,10 @@ enum Nf {
29392939
#undef INSN
29402940

29412941
// --------------------------
2942-
// addiw -> c.addiw
29432942
#define INSN(NAME) \
29442943
void NAME(Register Rd, Register Rs1, int32_t imm) { \
2945-
if (check_rvc() && (Rd == Rs1 && Rd != x0 && is_imm_in_range(imm, 6, 0))) { \
2944+
/* addiw -> c.addiw */ \
2945+
if (do_compress() && (Rd == Rs1 && Rd != x0 && is_imm_in_range(imm, 6, 0))) { \
29462946
c_addiw(Rd, imm); \
29472947
return; \
29482948
} \
@@ -2954,10 +2954,10 @@ enum Nf {
29542954
#undef INSN
29552955

29562956
// --------------------------
2957-
// and_imm12 -> c.andi
29582957
#define INSN(NAME) \
29592958
void NAME(Register Rd, Register Rs1, int32_t imm) { \
2960-
if (check_rvc() && \
2959+
/* and_imm12 -> c.andi */ \
2960+
if (do_compress() && \
29612961
(Rd == Rs1 && Rd->is_compressed_valid() && is_imm_in_range(imm, 6, 0))) { \
29622962
c_andi(Rd, imm); \
29632963
return; \
@@ -2972,10 +2972,10 @@ enum Nf {
29722972
// --------------------------
29732973
// Shift Immediate Instructions
29742974
// --------------------------
2975-
// slli -> c.slli
29762975
#define INSN(NAME) \
29772976
void NAME(Register Rd, Register Rs1, unsigned shamt) { \
2978-
if (check_rvc() && (Rd == Rs1 && Rd != x0 && shamt != 0)) { \
2977+
/* slli -> c.slli */ \
2978+
if (do_compress() && (Rd == Rs1 && Rd != x0 && shamt != 0)) { \
29792979
c_slli(Rd, shamt); \
29802980
return; \
29812981
} \
@@ -2987,10 +2987,10 @@ enum Nf {
29872987
#undef INSN
29882988

29892989
// --------------------------
2990-
// srai/srli -> c.srai/c.srli
29912990
#define INSN(NAME, C_NAME, NORMAL_NAME) \
29922991
void NAME(Register Rd, Register Rs1, unsigned shamt) { \
2993-
if (check_rvc() && (Rd == Rs1 && Rd->is_compressed_valid() && shamt != 0)) { \
2992+
/* srai/srli -> c.srai/c.srli */ \
2993+
if (do_compress() && (Rd == Rs1 && Rd->is_compressed_valid() && shamt != 0)) { \
29942994
C_NAME(Rd, shamt); \
29952995
return; \
29962996
} \
@@ -3005,10 +3005,10 @@ enum Nf {
30053005
// --------------------------
30063006
// Upper Immediate Instruction
30073007
// --------------------------
3008-
// lui -> c.lui
30093008
#define INSN(NAME) \
30103009
void NAME(Register Rd, int32_t imm) { \
3011-
if (check_rvc() && (Rd != x0 && Rd != x2 && imm != 0 && is_imm_in_range(imm, 18, 0))) { \
3010+
/* lui -> c.lui */ \
3011+
if (do_compress() && (Rd != x0 && Rd != x2 && imm != 0 && is_imm_in_range(imm, 18, 0))) { \
30123012
c_lui(Rd, imm); \
30133013
return; \
30143014
} \
@@ -3021,7 +3021,8 @@ enum Nf {
30213021

30223022
#define INSN(NAME) \
30233023
void NAME() { \
3024-
if (check_rvc()) { \
3024+
/* The illegal instruction in RVC is presented by a 16-bit 0. */ \
3025+
if (do_compress()) { \
30253026
emit_int16(0); \
30263027
return; \
30273028
} \

‎src/hotspot/cpu/riscv/globals_riscv.hpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,6 @@ define_pd_global(intx, InlineSmallCode, 1000);
9292
"Avoid generating unaligned memory accesses") \
9393
product(bool, UseRVV, false, EXPERIMENTAL, "Use RVV instructions") \
9494
product(bool, UseRVB, false, EXPERIMENTAL, "Use RVB instructions") \
95-
product(bool, UseRVC, false, EXPERIMENTAL, "Use RVC instructions") \
95+
product(bool, UseRVC, false, EXPERIMENTAL, "Use RVC instructions")
9696

9797
#endif // CPU_RISCV_GLOBALS_RISCV_HPP

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