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Fei Yang
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Merge branch 'master' into riscv-port
2 parents 8e0df0d + 4f607f2 commit 273291e

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‎src/hotspot/cpu/aarch64/aarch64_sve.ad‎

Lines changed: 33 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -411,21 +411,22 @@ instruct storeV_masked_partial(vReg src, vmemA mem, pRegGov pg, pRegGov pgtmp, r
411411
ins_pipe(pipe_slow);
412412
%}
413413

414-
// maskAll
414+
// maskAll (full or partial predicate size)
415415

416416
instruct vmaskAll_immI(pRegGov dst, immI src) %{
417417
predicate(UseSVE > 0);
418418
match(Set dst (MaskAll src));
419419
ins_cost(SVE_COST);
420-
format %{ "sve_ptrue/sve_pfalse $dst\t# mask all (sve) (B/H/S)" %}
420+
format %{ "sve_ptrue_lanecnt/sve_pfalse $dst\t# mask all (sve) (B/H/S)" %}
421421
ins_encode %{
422422
int con = (int)$src$$constant;
423423
if (con == 0) {
424424
__ sve_pfalse(as_PRegister($dst$$reg));
425425
} else {
426426
assert(con == -1, "invalid constant value for mask");
427427
BasicType bt = Matcher::vector_element_basic_type(this);
428-
__ sve_ptrue(as_PRegister($dst$$reg), __ elemType_to_regVariant(bt));
428+
__ sve_ptrue_lanecnt(as_PRegister($dst$$reg), __ elemType_to_regVariant(bt),
429+
Matcher::vector_length(this));
429430
}
430431
%}
431432
ins_pipe(pipe_slow);
@@ -435,14 +436,22 @@ instruct vmaskAllI(pRegGov dst, iRegIorL2I src, vReg tmp, rFlagsReg cr) %{
435436
predicate(UseSVE > 0);
436437
match(Set dst (MaskAll src));
437438
effect(TEMP tmp, KILL cr);
438-
ins_cost(2 * SVE_COST);
439+
ins_cost(3 * SVE_COST);
439440
format %{ "sve_dup $tmp, $src\n\t"
440-
"sve_cmpne $dst, $tmp, 0\t# mask all (sve) (B/H/S)" %}
441+
"sve_ptrue_lanecnt $dst\n\t"
442+
"sve_cmpne $dst, $dst, $tmp, 0\t# mask all (sve) (B/H/S)" %}
441443
ins_encode %{
442444
BasicType bt = Matcher::vector_element_basic_type(this);
443445
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
446+
uint length_in_bytes = Matcher::vector_length_in_bytes(this);
444447
__ sve_dup(as_FloatRegister($tmp$$reg), size, as_Register($src$$reg));
445-
__ sve_cmp(Assembler::NE, as_PRegister($dst$$reg), size, ptrue, as_FloatRegister($tmp$$reg), 0);
448+
if (length_in_bytes < MaxVectorSize) {
449+
__ sve_ptrue_lanecnt(as_PRegister($dst$$reg), size, Matcher::vector_length(this));
450+
__ sve_cmp(Assembler::NE, as_PRegister($dst$$reg), size,
451+
as_PRegister($dst$$reg), as_FloatRegister($tmp$$reg), 0);
452+
} else {
453+
__ sve_cmp(Assembler::NE, as_PRegister($dst$$reg), size, ptrue, as_FloatRegister($tmp$$reg), 0);
454+
}
446455
%}
447456
ins_pipe(pipe_slow);
448457
%}
@@ -451,15 +460,16 @@ instruct vmaskAll_immL(pRegGov dst, immL src) %{
451460
predicate(UseSVE > 0);
452461
match(Set dst (MaskAll src));
453462
ins_cost(SVE_COST);
454-
format %{ "sve_ptrue/sve_pfalse $dst\t# mask all (sve) (D)" %}
463+
format %{ "sve_ptrue_lanecnt/sve_pfalse $dst\t# mask all (sve) (D)" %}
455464
ins_encode %{
456465
long con = (long)$src$$constant;
457466
if (con == 0) {
458467
__ sve_pfalse(as_PRegister($dst$$reg));
459468
} else {
460469
assert(con == -1, "invalid constant value for mask");
461470
BasicType bt = Matcher::vector_element_basic_type(this);
462-
__ sve_ptrue(as_PRegister($dst$$reg), __ elemType_to_regVariant(bt));
471+
__ sve_ptrue_lanecnt(as_PRegister($dst$$reg), __ elemType_to_regVariant(bt),
472+
Matcher::vector_length(this));
463473
}
464474
%}
465475
ins_pipe(pipe_slow);
@@ -469,14 +479,22 @@ instruct vmaskAllL(pRegGov dst, iRegL src, vReg tmp, rFlagsReg cr) %{
469479
predicate(UseSVE > 0);
470480
match(Set dst (MaskAll src));
471481
effect(TEMP tmp, KILL cr);
472-
ins_cost(2 * SVE_COST);
482+
ins_cost(3 * SVE_COST);
473483
format %{ "sve_dup $tmp, $src\n\t"
474-
"sve_cmpne $dst, $tmp, 0\t# mask all (sve) (D)" %}
484+
"sve_ptrue_lanecnt $dst\n\t"
485+
"sve_cmpne $dst, $dst, $tmp, 0\t# mask all (sve) (D)" %}
475486
ins_encode %{
476487
BasicType bt = Matcher::vector_element_basic_type(this);
477488
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
489+
uint length_in_bytes = Matcher::vector_length_in_bytes(this);
478490
__ sve_dup(as_FloatRegister($tmp$$reg), size, as_Register($src$$reg));
479-
__ sve_cmp(Assembler::NE, as_PRegister($dst$$reg), size, ptrue, as_FloatRegister($tmp$$reg), 0);
491+
if (length_in_bytes < MaxVectorSize) {
492+
__ sve_ptrue_lanecnt(as_PRegister($dst$$reg), size, Matcher::vector_length(this));
493+
__ sve_cmp(Assembler::NE, as_PRegister($dst$$reg), size,
494+
as_PRegister($dst$$reg), as_FloatRegister($tmp$$reg), 0);
495+
} else {
496+
__ sve_cmp(Assembler::NE, as_PRegister($dst$$reg), size, ptrue, as_FloatRegister($tmp$$reg), 0);
497+
}
480498
%}
481499
ins_pipe(pipe_slow);
482500
%}
@@ -3084,6 +3102,7 @@ instruct reduce_maxF_masked(vRegF dst, vRegF src1, vReg src2, pRegGov pg) %{
30843102
n->in(1)->in(2)->bottom_type()->is_vect()->length_in_bytes() == MaxVectorSize);
30853103
match(Set dst (MaxReductionV (Binary src1 src2) pg));
30863104
ins_cost(SVE_COST);
3105+
effect(TEMP_DEF dst);
30873106
format %{ "sve_reduce_maxF $dst, $src1, $pg, $src2\t# maxF reduction predicated (sve)" %}
30883107
ins_encode %{
30893108
__ sve_fmaxv(as_FloatRegister($dst$$reg), __ S, as_PRegister($pg$$reg), as_FloatRegister($src2$$reg));
@@ -3098,6 +3117,7 @@ instruct reduce_maxD_masked(vRegD dst, vRegD src1, vReg src2, pRegGov pg) %{
30983117
n->in(1)->in(2)->bottom_type()->is_vect()->length_in_bytes() == MaxVectorSize);
30993118
match(Set dst (MaxReductionV (Binary src1 src2) pg));
31003119
ins_cost(SVE_COST);
3120+
effect(TEMP_DEF dst);
31013121
format %{ "sve_reduce_maxD $dst, $src1, $pg, $src2\t# maxD reduction predicated (sve)" %}
31023122
ins_encode %{
31033123
__ sve_fmaxv(as_FloatRegister($dst$$reg), __ D, as_PRegister($pg$$reg), as_FloatRegister($src2$$reg));
@@ -3380,6 +3400,7 @@ instruct reduce_minF_masked(vRegF dst, vRegF src1, vReg src2, pRegGov pg) %{
33803400
n->in(1)->in(2)->bottom_type()->is_vect()->length_in_bytes() == MaxVectorSize);
33813401
match(Set dst (MinReductionV (Binary src1 src2) pg));
33823402
ins_cost(SVE_COST);
3403+
effect(TEMP_DEF dst);
33833404
format %{ "sve_reduce_minF $dst, $src1, $pg, $src2\t# minF reduction predicated (sve)" %}
33843405
ins_encode %{
33853406
__ sve_fminv(as_FloatRegister($dst$$reg), __ S, as_PRegister($pg$$reg), as_FloatRegister($src2$$reg));
@@ -3394,6 +3415,7 @@ instruct reduce_minD_masked(vRegD dst, vRegD src1, vReg src2, pRegGov pg) %{
33943415
n->in(1)->in(2)->bottom_type()->is_vect()->length_in_bytes() == MaxVectorSize);
33953416
match(Set dst (MinReductionV (Binary src1 src2) pg));
33963417
ins_cost(SVE_COST);
3418+
effect(TEMP_DEF dst);
33973419
format %{ "sve_reduce_minD $dst, $src1, $pg, $src2\t# minD reduction predicated (sve)" %}
33983420
ins_encode %{
33993421
__ sve_fminv(as_FloatRegister($dst$$reg), __ D, as_PRegister($pg$$reg), as_FloatRegister($src2$$reg));

‎src/hotspot/cpu/aarch64/aarch64_sve_ad.m4‎

Lines changed: 16 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -356,15 +356,16 @@ instruct vmaskAll_imm$1(pRegGov dst, imm$1 src) %{
356356
predicate(UseSVE > 0);
357357
match(Set dst (MaskAll src));
358358
ins_cost(SVE_COST);
359-
format %{ "sve_ptrue/sve_pfalse $dst\t# mask all (sve) ($2)" %}
359+
format %{ "sve_ptrue_lanecnt/sve_pfalse $dst\t# mask all (sve) ($2)" %}
360360
ins_encode %{
361361
ifelse($1, `I', int, long) con = (ifelse($1, `I', int, long))$src$$constant;
362362
if (con == 0) {
363363
__ sve_pfalse(as_PRegister($dst$$reg));
364364
} else {
365365
assert(con == -1, "invalid constant value for mask");
366366
BasicType bt = Matcher::vector_element_basic_type(this);
367-
__ sve_ptrue(as_PRegister($dst$$reg), __ elemType_to_regVariant(bt));
367+
__ sve_ptrue_lanecnt(as_PRegister($dst$$reg), __ elemType_to_regVariant(bt),
368+
Matcher::vector_length(this));
368369
}
369370
%}
370371
ins_pipe(pipe_slow);
@@ -377,19 +378,27 @@ instruct vmaskAll$1(pRegGov dst, ifelse($1, `I', iRegIorL2I, iRegL) src, vReg tm
377378
predicate(UseSVE > 0);
378379
match(Set dst (MaskAll src));
379380
effect(TEMP tmp, KILL cr);
380-
ins_cost(2 * SVE_COST);
381+
ins_cost(3 * SVE_COST);
381382
format %{ "sve_dup $tmp, $src\n\t"
382-
"sve_cmpne $dst, $tmp, 0\t# mask all (sve) ($2)" %}
383+
"sve_ptrue_lanecnt $dst\n\t"
384+
"sve_cmpne $dst, $dst, $tmp, 0\t# mask all (sve) ($2)" %}
383385
ins_encode %{
384386
BasicType bt = Matcher::vector_element_basic_type(this);
385387
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
388+
uint length_in_bytes = Matcher::vector_length_in_bytes(this);
386389
__ sve_dup(as_FloatRegister($tmp$$reg), size, as_Register($src$$reg));
387-
__ sve_cmp(Assembler::NE, as_PRegister($dst$$reg), size, ptrue, as_FloatRegister($tmp$$reg), 0);
390+
if (length_in_bytes < MaxVectorSize) {
391+
__ sve_ptrue_lanecnt(as_PRegister($dst$$reg), size, Matcher::vector_length(this));
392+
__ sve_cmp(Assembler::NE, as_PRegister($dst$$reg), size,
393+
as_PRegister($dst$$reg), as_FloatRegister($tmp$$reg), 0);
394+
} else {
395+
__ sve_cmp(Assembler::NE, as_PRegister($dst$$reg), size, ptrue, as_FloatRegister($tmp$$reg), 0);
396+
}
388397
%}
389398
ins_pipe(pipe_slow);
390399
%}')dnl
391400
dnl
392-
// maskAll
401+
// maskAll (full or partial predicate size)
393402
MASKALL_IMM(I, B/H/S)
394403
MASKALL(I, B/H/S)
395404
MASKALL_IMM(L, D)
@@ -1807,6 +1816,7 @@ instruct reduce_$1$2_masked($5 dst, $5 src1, vReg src2, pRegGov pg) %{
18071816
n->in(1)->in(2)->bottom_type()->is_vect()->length_in_bytes() == MaxVectorSize);
18081817
match(Set dst (translit($1, `m', `M')ReductionV (Binary src1 src2) pg));
18091818
ins_cost(SVE_COST);
1819+
effect(TEMP_DEF dst);
18101820
format %{ "sve_reduce_$1$2 $dst, $src1, $pg, $src2\t# $1$2 reduction predicated (sve)" %}
18111821
ins_encode %{
18121822
__ sve_f$1v(as_FloatRegister($dst$$reg), __ $4, as_PRegister($pg$$reg), as_FloatRegister($src2$$reg));

‎src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp‎

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1232,3 +1232,39 @@ void C2_MacroAssembler::sve_reduce_integral(int opc, Register dst, BasicType bt,
12321232
}
12331233
}
12341234
}
1235+
1236+
// Set elements of the dst predicate to true if the element number is
1237+
// in the range of [0, lane_cnt), or to false otherwise.
1238+
void C2_MacroAssembler::sve_ptrue_lanecnt(PRegister dst, SIMD_RegVariant size, int lane_cnt) {
1239+
assert(size != Q, "invalid size");
1240+
switch(lane_cnt) {
1241+
case 1: /* VL1 */
1242+
case 2: /* VL2 */
1243+
case 3: /* VL3 */
1244+
case 4: /* VL4 */
1245+
case 5: /* VL5 */
1246+
case 6: /* VL6 */
1247+
case 7: /* VL7 */
1248+
case 8: /* VL8 */
1249+
sve_ptrue(dst, size, lane_cnt);
1250+
break;
1251+
case 16:
1252+
sve_ptrue(dst, size, /* VL16 */ 0b01001);
1253+
break;
1254+
case 32:
1255+
sve_ptrue(dst, size, /* VL32 */ 0b01010);
1256+
break;
1257+
case 64:
1258+
sve_ptrue(dst, size, /* VL64 */ 0b01011);
1259+
break;
1260+
case 128:
1261+
sve_ptrue(dst, size, /* VL128 */ 0b01100);
1262+
break;
1263+
case 256:
1264+
sve_ptrue(dst, size, /* VL256 */ 0b01101);
1265+
break;
1266+
default:
1267+
assert(false, "unsupported");
1268+
ShouldNotReachHere();
1269+
}
1270+
}

‎src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.hpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,10 @@
8888
void sve_reduce_integral(int opc, Register dst, BasicType bt, Register src1,
8989
FloatRegister src2, PRegister pg, FloatRegister tmp);
9090

91+
// Set elements of the dst predicate to true if the element number is
92+
// in the range of [0, lane_cnt), or to false otherwise.
93+
void sve_ptrue_lanecnt(PRegister dst, SIMD_RegVariant size, int lane_cnt);
94+
9195
// Generate predicate through whilelo, by comparing ZR with an unsigned
9296
// immediate. rscratch1 will be clobbered.
9397
inline void sve_whilelo_zr_imm(PRegister pd, SIMD_RegVariant size, uint imm) {

‎src/hotspot/cpu/aarch64/spin_wait_aarch64.hpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2021, Amazon.com Inc. or its affiliates. All rights reserved.
2+
* Copyright Amazon.com Inc. or its affiliates. All Rights Reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it

‎src/hotspot/share/c1/c1_LIRGenerator.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -963,6 +963,14 @@ void LIRGenerator::move_to_phi(PhiResolver* resolver, Value cur_val, Value sux_v
963963
Phi* phi = sux_val->as_Phi();
964964
// cur_val can be null without phi being null in conjunction with inlining
965965
if (phi != NULL && cur_val != NULL && cur_val != phi && !phi->is_illegal()) {
966+
if (phi->is_local()) {
967+
for (int i = 0; i < phi->operand_count(); i++) {
968+
Value op = phi->operand_at(i);
969+
if (op != NULL && op->type()->is_illegal()) {
970+
bailout("illegal phi operand");
971+
}
972+
}
973+
}
966974
Phi* cur_phi = cur_val->as_Phi();
967975
if (cur_phi != NULL && cur_phi->is_illegal()) {
968976
// Phi and local would need to get invalidated

‎src/hotspot/share/gc/g1/g1OldGenAllocationTracker.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2020, Amazon.com, Inc. or its affiliates. All rights reserved.
2+
* Copyright Amazon.com Inc. or its affiliates. All Rights Reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it

‎src/hotspot/share/gc/g1/g1OldGenAllocationTracker.hpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2020, Amazon.com, Inc. or its affiliates. All rights reserved.
2+
* Copyright Amazon.com Inc. or its affiliates. All Rights Reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it

‎src/java.base/share/man/java.1‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1541,6 +1541,31 @@ and its committed regions.
15411541
.RE
15421542
.RE
15431543
.TP
1544+
.B \f[CB]\-XX:+NeverActAsServerClassMachine\f[R]
1545+
Enable the "Client VM emulation" mode which only uses the C1 JIT
1546+
compiler, a 32Mb CodeCache and the Serial GC.
1547+
The maximum amount of memory that the JVM may use (controlled by the
1548+
\f[CB]\-XX:MaxRAM=n\f[R] flag) is set to 1GB by default.
1549+
The string "emulated\-client" is added to the JVM version string.
1550+
.RS
1551+
.PP
1552+
By default the flag is set to \f[CB]true\f[R] only on Windows in 32\-bit
1553+
mode and \f[CB]false\f[R] in all other cases.
1554+
.PP
1555+
The "Client VM emulation" mode will not be enabled if any of the
1556+
following flags are used on the command line:
1557+
.IP
1558+
.nf
1559+
\f[CB]
1560+
\-XX:{+|\-}TieredCompilation
1561+
\-XX:CompilationMode=mode
1562+
\-XX:TieredStopAtLevel=n
1563+
\-XX:{+|\-}EnableJVMCI
1564+
\-XX:{+|\-}UseJVMCICompiler
1565+
\f[R]
1566+
.fi
1567+
.RE
1568+
.TP
15441569
.B \f[CB]\-XX:ObjectAlignmentInBytes=\f[R]\f[I]alignment\f[R]
15451570
Sets the memory alignment of Java objects (in bytes).
15461571
By default, the value is set to 8 bytes.

‎test/hotspot/gtest/aarch64/aarch64-asmtest.py‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1723,9 +1723,22 @@ def generate(kind, names):
17231723
["bic", "__ sve_bic(p10, p7, p9, p11);", "bic\tp10.b, p7/z, p9.b, p11.b"],
17241724
["ptest", "__ sve_ptest(p7, p1);", "ptest\tp7, p1.b"],
17251725
["ptrue", "__ sve_ptrue(p1, __ B);", "ptrue\tp1.b"],
1726+
["ptrue", "__ sve_ptrue(p1, __ B, 0b00001);", "ptrue\tp1.b, vl1"],
1727+
["ptrue", "__ sve_ptrue(p1, __ B, 0b00101);", "ptrue\tp1.b, vl5"],
1728+
["ptrue", "__ sve_ptrue(p1, __ B, 0b01001);", "ptrue\tp1.b, vl16"],
1729+
["ptrue", "__ sve_ptrue(p1, __ B, 0b01101);", "ptrue\tp1.b, vl256"],
17261730
["ptrue", "__ sve_ptrue(p2, __ H);", "ptrue\tp2.h"],
1731+
["ptrue", "__ sve_ptrue(p2, __ H, 0b00010);", "ptrue\tp2.h, vl2"],
1732+
["ptrue", "__ sve_ptrue(p2, __ H, 0b00110);", "ptrue\tp2.h, vl6"],
1733+
["ptrue", "__ sve_ptrue(p2, __ H, 0b01010);", "ptrue\tp2.h, vl32"],
17271734
["ptrue", "__ sve_ptrue(p3, __ S);", "ptrue\tp3.s"],
1735+
["ptrue", "__ sve_ptrue(p3, __ S, 0b00011);", "ptrue\tp3.s, vl3"],
1736+
["ptrue", "__ sve_ptrue(p3, __ S, 0b00111);", "ptrue\tp3.s, vl7"],
1737+
["ptrue", "__ sve_ptrue(p3, __ S, 0b01011);", "ptrue\tp3.s, vl64"],
17281738
["ptrue", "__ sve_ptrue(p4, __ D);", "ptrue\tp4.d"],
1739+
["ptrue", "__ sve_ptrue(p4, __ D, 0b00100);", "ptrue\tp4.d, vl4"],
1740+
["ptrue", "__ sve_ptrue(p4, __ D, 0b01000);", "ptrue\tp4.d, vl8"],
1741+
["ptrue", "__ sve_ptrue(p4, __ D, 0b01100);", "ptrue\tp4.d, vl128"],
17291742
["pfalse", "__ sve_pfalse(p7);", "pfalse\tp7.b"],
17301743
["uzp1", "__ sve_uzp1(p0, __ B, p0, p1);", "uzp1\tp0.b, p0.b, p1.b"],
17311744
["uzp1", "__ sve_uzp1(p0, __ H, p0, p1);", "uzp1\tp0.h, p0.h, p1.h"],

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