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zhengxiaolinXzhengxiaolinX
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Rename misc functions and change the positions of some comments
1 parent 2ecdc92 commit 6102220

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2 files changed

+48
-47
lines changed

2 files changed

+48
-47
lines changed

‎src/hotspot/cpu/riscv/assembler_riscv.hpp‎

Lines changed: 47 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -1342,15 +1342,15 @@ enum operand_size { int8, int16, int32, uint32, int64 };
13421342
class CompressibleRegion : public StackObj {
13431343
protected:
13441344
Assembler *_masm;
1345-
bool _prev_in_compressible_region;
1345+
bool _saved_in_compressible_region;
13461346
public:
13471347
CompressibleRegion(Assembler *_masm)
13481348
: _masm(_masm)
1349-
, _prev_in_compressible_region(_masm->in_compressible_region()) {
1349+
, _saved_in_compressible_region(_masm->in_compressible_region()) {
13501350
_masm->set_in_compressible_region(true);
13511351
}
13521352
~CompressibleRegion() {
1353-
_masm->set_in_compressible_region(_prev_in_compressible_region);
1353+
_masm->set_in_compressible_region(_saved_in_compressible_region);
13541354
}
13551355
};
13561356

@@ -1837,10 +1837,10 @@ enum operand_size { int8, int16, int32, uint32, int64 };
18371837
// --------------------------
18381838
// Register instructions
18391839
// --------------------------
1840-
// add -> c.add
18411840
#define INSN(NAME) \
18421841
void NAME(Register Rd, Register Rs1, Register Rs2) { \
1843-
if (check_rvc()) { \
1842+
/* add -> c.add */ \
1843+
if (do_compress()) { \
18441844
Register src = noreg; \
18451845
if (Rs1 != x0 && Rs2 != x0 && ((src = Rs1, Rs2 == Rd) || (src = Rs2, Rs1 == Rd))) { \
18461846
c_add(Rd, src); \
@@ -1855,10 +1855,10 @@ enum operand_size { int8, int16, int32, uint32, int64 };
18551855
#undef INSN
18561856

18571857
// --------------------------
1858-
// sub/subw -> c.sub/c.subw
18591858
#define INSN(NAME, C_NAME, NORMAL_NAME) \
18601859
void NAME(Register Rd, Register Rs1, Register Rs2) { \
1861-
if (check_rvc() && \
1860+
/* sub/subw -> c.sub/c.subw */ \
1861+
if (do_compress() && \
18621862
(Rd == Rs1 && Rd->is_compressed_valid() && Rs2->is_compressed_valid())) { \
18631863
C_NAME(Rd, Rs2); \
18641864
return; \
@@ -1872,10 +1872,10 @@ enum operand_size { int8, int16, int32, uint32, int64 };
18721872
#undef INSN
18731873

18741874
// --------------------------
1875-
// xor/or/and/addw -> c.xor/c.or/c.and/c.addw
18761875
#define INSN(NAME, C_NAME, NORMAL_NAME) \
18771876
void NAME(Register Rd, Register Rs1, Register Rs2) { \
1878-
if (check_rvc()) { \
1877+
/* and/or/xor/addw -> c.and/c.or/c.xor/c.addw */ \
1878+
if (do_compress()) { \
18791879
Register src = noreg; \
18801880
if (Rs1->is_compressed_valid() && Rs2->is_compressed_valid() && \
18811881
((src = Rs1, Rs2 == Rd) || (src = Rs2, Rs1 == Rd))) { \
@@ -1895,7 +1895,7 @@ enum operand_size { int8, int16, int32, uint32, int64 };
18951895

18961896
private:
18971897
// some helper functions
1898-
bool check_rvc() const {
1898+
bool do_compress() const {
18991899
return UseRVC && in_compressible_region();
19001900
}
19011901

@@ -1941,10 +1941,10 @@ enum operand_size { int8, int16, int32, uint32, int64 };
19411941
// --------------------------
19421942
// Load/store register
19431943
// --------------------------
1944-
// lw -> c.lwsp/c.lw
19451944
#define INSN(NAME) \
19461945
void NAME(Register Rd, Register Rs, const int32_t offset) { \
1947-
if (check_rvc()) { \
1946+
/* lw -> c.lwsp/c.lw */ \
1947+
if (do_compress()) { \
19481948
if (is_c_lwswsp(Rs, Rd, offset, true)) { \
19491949
c_lwsp(Rd, offset); \
19501950
return; \
@@ -1961,10 +1961,10 @@ enum operand_size { int8, int16, int32, uint32, int64 };
19611961
#undef INSN
19621962

19631963
// --------------------------
1964-
// ld -> c.ldsp/c.ld
19651964
#define INSN(NAME) \
19661965
void NAME(Register Rd, Register Rs, const int32_t offset) { \
1967-
if (check_rvc()) { \
1966+
/* ld -> c.ldsp/c.ld */ \
1967+
if (do_compress()) { \
19681968
if (is_c_ldsdsp(Rs, Rd, offset, true)) { \
19691969
c_ldsp(Rd, offset); \
19701970
return; \
@@ -1981,10 +1981,10 @@ enum operand_size { int8, int16, int32, uint32, int64 };
19811981
#undef INSN
19821982

19831983
// --------------------------
1984-
// fld -> c.fldsp/c.fld
19851984
#define INSN(NAME) \
19861985
void NAME(FloatRegister Rd, Register Rs, const int32_t offset) { \
1987-
if (check_rvc()) { \
1986+
/* fld -> c.fldsp/c.fld */ \
1987+
if (do_compress()) { \
19881988
if (is_c_fldsdsp(Rs, offset)) { \
19891989
c_fldsp(Rd, offset); \
19901990
return; \
@@ -2001,10 +2001,10 @@ enum operand_size { int8, int16, int32, uint32, int64 };
20012001
#undef INSN
20022002

20032003
// --------------------------
2004-
// sd -> c.sdsp/c.sd
20052004
#define INSN(NAME) \
20062005
void NAME(Register Rd, Register Rs, const int32_t offset) { \
2007-
if (check_rvc()) { \
2006+
/* sd -> c.sdsp/c.sd */ \
2007+
if (do_compress()) { \
20082008
if (is_c_ldsdsp(Rs, Rd, offset, false)) { \
20092009
c_sdsp(Rd, offset); \
20102010
return; \
@@ -2021,10 +2021,10 @@ enum operand_size { int8, int16, int32, uint32, int64 };
20212021
#undef INSN
20222022

20232023
// --------------------------
2024-
// sw -> c.swsp/c.sw
20252024
#define INSN(NAME) \
20262025
void NAME(Register Rd, Register Rs, const int32_t offset) { \
2027-
if (check_rvc()) { \
2026+
/* sw -> c.swsp/c.sw */ \
2027+
if (do_compress()) { \
20282028
if (is_c_lwswsp(Rs, Rd, offset, false)) { \
20292029
c_swsp(Rd, offset); \
20302030
return; \
@@ -2041,10 +2041,10 @@ enum operand_size { int8, int16, int32, uint32, int64 };
20412041
#undef INSN
20422042

20432043
// --------------------------
2044-
// fsd -> c.fsdsp/c.fsd
20452044
#define INSN(NAME) \
20462045
void NAME(FloatRegister Rd, Register Rs, const int32_t offset) { \
2047-
if (check_rvc()) { \
2046+
/* fsd -> c.fsdsp/c.fsd */ \
2047+
if (do_compress()) { \
20482048
if (is_c_fldsdsp(Rs, offset)) { \
20492049
c_fsdsp(Rd, offset); \
20502050
return; \
@@ -2063,11 +2063,10 @@ enum operand_size { int8, int16, int32, uint32, int64 };
20632063
// --------------------------
20642064
// Conditional branch instructions
20652065
// --------------------------
2066-
// beq/bne -> c.beqz/c.bnez
2067-
20682066
#define INSN(NAME, C_NAME, NORMAL_NAME) \
20692067
void NAME(Register Rs1, Register Rs2, const int64_t offset) { \
2070-
if (check_rvc() && \
2068+
/* beq/bne -> c.beqz/c.bnez */ \
2069+
if (do_compress() && \
20712070
(offset != 0 && Rs2 == x0 && Rs1->is_compressed_valid() && \
20722071
is_imm_in_range(offset, 8, 1))) { \
20732072
C_NAME(Rs1, offset); \
@@ -2084,10 +2083,10 @@ enum operand_size { int8, int16, int32, uint32, int64 };
20842083
// --------------------------
20852084
// Unconditional branch instructions
20862085
// --------------------------
2087-
// jal -> c.j
20882086
#define INSN(NAME) \
20892087
void NAME(Register Rd, const int32_t offset) { \
2090-
if (check_rvc() && offset != 0 && Rd == x0 && is_imm_in_range(offset, 11, 1)) { \
2088+
/* jal -> c.j */ \
2089+
if (do_compress() && offset != 0 && Rd == x0 && is_imm_in_range(offset, 11, 1)) { \
20912090
c_j(offset); \
20922091
return; \
20932092
} \
@@ -2099,10 +2098,10 @@ enum operand_size { int8, int16, int32, uint32, int64 };
20992098
#undef INSN
21002099

21012100
// --------------------------
2102-
// jalr -> c.jr/c.jalr
21032101
#define INSN(NAME) \
21042102
void NAME(Register Rd, Register Rs, const int32_t offset) { \
2105-
if (check_rvc() && (offset == 0 && Rs != x0)) { \
2103+
/* jalr -> c.jr/c.jalr */ \
2104+
if (do_compress() && (offset == 0 && Rs != x0)) { \
21062105
if (Rd == x1) { \
21072106
c_jalr(Rs); \
21082107
return; \
@@ -2121,10 +2120,10 @@ enum operand_size { int8, int16, int32, uint32, int64 };
21212120
// --------------------------
21222121
// Miscellaneous Instructions
21232122
// --------------------------
2124-
// ebreak -> c.ebreak
21252123
#define INSN(NAME) \
21262124
void NAME() { \
2127-
if (check_rvc()) { \
2125+
/* ebreak -> c.ebreak */ \
2126+
if (do_compress()) { \
21282127
c_ebreak(); \
21292128
return; \
21302129
} \
@@ -2138,10 +2137,10 @@ enum operand_size { int8, int16, int32, uint32, int64 };
21382137
// --------------------------
21392138
// Immediate Instructions
21402139
// --------------------------
2141-
// li -> c.li
21422140
#define INSN(NAME) \
21432141
void NAME(Register Rd, int64_t imm) { \
2144-
if (check_rvc() && (is_imm_in_range(imm, 6, 0) && Rd != x0)) { \
2142+
/* li -> c.li */ \
2143+
if (do_compress() && (is_imm_in_range(imm, 6, 0) && Rd != x0)) { \
21452144
c_li(Rd, imm); \
21462145
return; \
21472146
} \
@@ -2152,10 +2151,11 @@ enum operand_size { int8, int16, int32, uint32, int64 };
21522151

21532152
#undef INSN
21542153

2155-
// addi -> c.addi/c.nop/c.mv/c.addi16sp/c.addi4spn.
2154+
// --------------------------
21562155
#define INSN(NAME) \
21572156
void NAME(Register Rd, Register Rs1, int32_t imm) { \
2158-
if (check_rvc()) { \
2157+
/* addi -> c.addi/c.nop/c.mv/c.addi16sp/c.addi4spn */ \
2158+
if (do_compress()) { \
21592159
if (Rd == Rs1 && is_imm_in_range(imm, 6, 0)) { \
21602160
c_addi(Rd, imm); \
21612161
return; \
@@ -2180,10 +2180,10 @@ enum operand_size { int8, int16, int32, uint32, int64 };
21802180
#undef INSN
21812181

21822182
// --------------------------
2183-
// addiw -> c.addiw
21842183
#define INSN(NAME) \
21852184
void NAME(Register Rd, Register Rs1, int32_t imm) { \
2186-
if (check_rvc() && (Rd == Rs1 && Rd != x0 && is_imm_in_range(imm, 6, 0))) { \
2185+
/* addiw -> c.addiw */ \
2186+
if (do_compress() && (Rd == Rs1 && Rd != x0 && is_imm_in_range(imm, 6, 0))) { \
21872187
c_addiw(Rd, imm); \
21882188
return; \
21892189
} \
@@ -2195,10 +2195,10 @@ enum operand_size { int8, int16, int32, uint32, int64 };
21952195
#undef INSN
21962196

21972197
// --------------------------
2198-
// and_imm12 -> c.andi
21992198
#define INSN(NAME) \
22002199
void NAME(Register Rd, Register Rs1, int32_t imm) { \
2201-
if (check_rvc() && \
2200+
/* and_imm12 -> c.andi */ \
2201+
if (do_compress() && \
22022202
(Rd == Rs1 && Rd->is_compressed_valid() && is_imm_in_range(imm, 6, 0))) { \
22032203
c_andi(Rd, imm); \
22042204
return; \
@@ -2213,10 +2213,10 @@ enum operand_size { int8, int16, int32, uint32, int64 };
22132213
// --------------------------
22142214
// Shift Immediate Instructions
22152215
// --------------------------
2216-
// slli -> c.slli
22172216
#define INSN(NAME) \
22182217
void NAME(Register Rd, Register Rs1, unsigned shamt) { \
2219-
if (check_rvc() && (Rd == Rs1 && Rd != x0 && shamt != 0)) { \
2218+
/* slli -> c.slli */ \
2219+
if (do_compress() && (Rd == Rs1 && Rd != x0 && shamt != 0)) { \
22202220
c_slli(Rd, shamt); \
22212221
return; \
22222222
} \
@@ -2228,10 +2228,10 @@ enum operand_size { int8, int16, int32, uint32, int64 };
22282228
#undef INSN
22292229

22302230
// --------------------------
2231-
// srai/srli -> c.srai/c.srli
22322231
#define INSN(NAME, C_NAME, NORMAL_NAME) \
22332232
void NAME(Register Rd, Register Rs1, unsigned shamt) { \
2234-
if (check_rvc() && (Rd == Rs1 && Rd->is_compressed_valid() && shamt != 0)) { \
2233+
/* srai/srli -> c.srai/c.srli */ \
2234+
if (do_compress() && (Rd == Rs1 && Rd->is_compressed_valid() && shamt != 0)) { \
22352235
C_NAME(Rd, shamt); \
22362236
return; \
22372237
} \
@@ -2246,10 +2246,10 @@ enum operand_size { int8, int16, int32, uint32, int64 };
22462246
// --------------------------
22472247
// Upper Immediate Instruction
22482248
// --------------------------
2249-
// lui -> c.lui
22502249
#define INSN(NAME) \
22512250
void NAME(Register Rd, int32_t imm) { \
2252-
if (check_rvc() && (Rd != x0 && Rd != x2 && imm != 0 && is_imm_in_range(imm, 18, 0))) { \
2251+
/* lui -> c.lui */ \
2252+
if (do_compress() && (Rd != x0 && Rd != x2 && imm != 0 && is_imm_in_range(imm, 18, 0))) { \
22532253
c_lui(Rd, imm); \
22542254
return; \
22552255
} \
@@ -2262,7 +2262,8 @@ enum operand_size { int8, int16, int32, uint32, int64 };
22622262

22632263
#define INSN(NAME) \
22642264
void NAME() { \
2265-
if (check_rvc()) { \
2265+
/* The illegal instruction in RVC is presented by a 16-bit 0. */ \
2266+
if (do_compress()) { \
22662267
emit_int16(0); \
22672268
return; \
22682269
} \

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