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zhengxiaolinXzhengxiaolinX
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Rename misc functions and change the positions of some comments
1 parent 2301d4a commit 6ffb88c

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2 files changed

+48
-47
lines changed

2 files changed

+48
-47
lines changed

‎src/hotspot/cpu/riscv/assembler_riscv.hpp‎

Lines changed: 47 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -2089,15 +2089,15 @@ enum Nf {
20892089
class CompressibleRegion : public StackObj {
20902090
protected:
20912091
Assembler *_masm;
2092-
bool _prev_in_compressible_region;
2092+
bool _saved_in_compressible_region;
20932093
public:
20942094
CompressibleRegion(Assembler *_masm)
20952095
: _masm(_masm)
2096-
, _prev_in_compressible_region(_masm->in_compressible_region()) {
2096+
, _saved_in_compressible_region(_masm->in_compressible_region()) {
20972097
_masm->set_in_compressible_region(true);
20982098
}
20992099
~CompressibleRegion() {
2100-
_masm->set_in_compressible_region(_prev_in_compressible_region);
2100+
_masm->set_in_compressible_region(_saved_in_compressible_region);
21012101
}
21022102
};
21032103

@@ -2584,10 +2584,10 @@ enum Nf {
25842584
// --------------------------
25852585
// Register instructions
25862586
// --------------------------
2587-
// add -> c.add
25882587
#define INSN(NAME) \
25892588
void NAME(Register Rd, Register Rs1, Register Rs2) { \
2590-
if (check_rvc()) { \
2589+
/* add -> c.add */ \
2590+
if (do_compress()) { \
25912591
Register src = noreg; \
25922592
if (Rs1 != x0 && Rs2 != x0 && ((src = Rs1, Rs2 == Rd) || (src = Rs2, Rs1 == Rd))) { \
25932593
c_add(Rd, src); \
@@ -2602,10 +2602,10 @@ enum Nf {
26022602
#undef INSN
26032603

26042604
// --------------------------
2605-
// sub/subw -> c.sub/c.subw
26062605
#define INSN(NAME, C_NAME, NORMAL_NAME) \
26072606
void NAME(Register Rd, Register Rs1, Register Rs2) { \
2608-
if (check_rvc() && \
2607+
/* sub/subw -> c.sub/c.subw */ \
2608+
if (do_compress() && \
26092609
(Rd == Rs1 && Rd->is_compressed_valid() && Rs2->is_compressed_valid())) { \
26102610
C_NAME(Rd, Rs2); \
26112611
return; \
@@ -2619,10 +2619,10 @@ enum Nf {
26192619
#undef INSN
26202620

26212621
// --------------------------
2622-
// xor/or/and/addw -> c.xor/c.or/c.and/c.addw
26232622
#define INSN(NAME, C_NAME, NORMAL_NAME) \
26242623
void NAME(Register Rd, Register Rs1, Register Rs2) { \
2625-
if (check_rvc()) { \
2624+
/* and/or/xor/addw -> c.and/c.or/c.xor/c.addw */ \
2625+
if (do_compress()) { \
26262626
Register src = noreg; \
26272627
if (Rs1->is_compressed_valid() && Rs2->is_compressed_valid() && \
26282628
((src = Rs1, Rs2 == Rd) || (src = Rs2, Rs1 == Rd))) { \
@@ -2642,7 +2642,7 @@ enum Nf {
26422642

26432643
private:
26442644
// some helper functions
2645-
bool check_rvc() const {
2645+
bool do_compress() const {
26462646
return UseRVC && in_compressible_region();
26472647
}
26482648

@@ -2688,10 +2688,10 @@ enum Nf {
26882688
// --------------------------
26892689
// Load/store register
26902690
// --------------------------
2691-
// lw -> c.lwsp/c.lw
26922691
#define INSN(NAME) \
26932692
void NAME(Register Rd, Register Rs, const int32_t offset) { \
2694-
if (check_rvc()) { \
2693+
/* lw -> c.lwsp/c.lw */ \
2694+
if (do_compress()) { \
26952695
if (is_c_lwswsp(Rs, Rd, offset, true)) { \
26962696
c_lwsp(Rd, offset); \
26972697
return; \
@@ -2708,10 +2708,10 @@ enum Nf {
27082708
#undef INSN
27092709

27102710
// --------------------------
2711-
// ld -> c.ldsp/c.ld
27122711
#define INSN(NAME) \
27132712
void NAME(Register Rd, Register Rs, const int32_t offset) { \
2714-
if (check_rvc()) { \
2713+
/* ld -> c.ldsp/c.ld */ \
2714+
if (do_compress()) { \
27152715
if (is_c_ldsdsp(Rs, Rd, offset, true)) { \
27162716
c_ldsp(Rd, offset); \
27172717
return; \
@@ -2728,10 +2728,10 @@ enum Nf {
27282728
#undef INSN
27292729

27302730
// --------------------------
2731-
// fld -> c.fldsp/c.fld
27322731
#define INSN(NAME) \
27332732
void NAME(FloatRegister Rd, Register Rs, const int32_t offset) { \
2734-
if (check_rvc()) { \
2733+
/* fld -> c.fldsp/c.fld */ \
2734+
if (do_compress()) { \
27352735
if (is_c_fldsdsp(Rs, offset)) { \
27362736
c_fldsp(Rd, offset); \
27372737
return; \
@@ -2748,10 +2748,10 @@ enum Nf {
27482748
#undef INSN
27492749

27502750
// --------------------------
2751-
// sd -> c.sdsp/c.sd
27522751
#define INSN(NAME) \
27532752
void NAME(Register Rd, Register Rs, const int32_t offset) { \
2754-
if (check_rvc()) { \
2753+
/* sd -> c.sdsp/c.sd */ \
2754+
if (do_compress()) { \
27552755
if (is_c_ldsdsp(Rs, Rd, offset, false)) { \
27562756
c_sdsp(Rd, offset); \
27572757
return; \
@@ -2768,10 +2768,10 @@ enum Nf {
27682768
#undef INSN
27692769

27702770
// --------------------------
2771-
// sw -> c.swsp/c.sw
27722771
#define INSN(NAME) \
27732772
void NAME(Register Rd, Register Rs, const int32_t offset) { \
2774-
if (check_rvc()) { \
2773+
/* sw -> c.swsp/c.sw */ \
2774+
if (do_compress()) { \
27752775
if (is_c_lwswsp(Rs, Rd, offset, false)) { \
27762776
c_swsp(Rd, offset); \
27772777
return; \
@@ -2788,10 +2788,10 @@ enum Nf {
27882788
#undef INSN
27892789

27902790
// --------------------------
2791-
// fsd -> c.fsdsp/c.fsd
27922791
#define INSN(NAME) \
27932792
void NAME(FloatRegister Rd, Register Rs, const int32_t offset) { \
2794-
if (check_rvc()) { \
2793+
/* fsd -> c.fsdsp/c.fsd */ \
2794+
if (do_compress()) { \
27952795
if (is_c_fldsdsp(Rs, offset)) { \
27962796
c_fsdsp(Rd, offset); \
27972797
return; \
@@ -2810,11 +2810,10 @@ enum Nf {
28102810
// --------------------------
28112811
// Conditional branch instructions
28122812
// --------------------------
2813-
// beq/bne -> c.beqz/c.bnez
2814-
28152813
#define INSN(NAME, C_NAME, NORMAL_NAME) \
28162814
void NAME(Register Rs1, Register Rs2, const int64_t offset) { \
2817-
if (check_rvc() && \
2815+
/* beq/bne -> c.beqz/c.bnez */ \
2816+
if (do_compress() && \
28182817
(offset != 0 && Rs2 == x0 && Rs1->is_compressed_valid() && \
28192818
is_imm_in_range(offset, 8, 1))) { \
28202819
C_NAME(Rs1, offset); \
@@ -2831,10 +2830,10 @@ enum Nf {
28312830
// --------------------------
28322831
// Unconditional branch instructions
28332832
// --------------------------
2834-
// jal -> c.j
28352833
#define INSN(NAME) \
28362834
void NAME(Register Rd, const int32_t offset) { \
2837-
if (check_rvc() && offset != 0 && Rd == x0 && is_imm_in_range(offset, 11, 1)) { \
2835+
/* jal -> c.j */ \
2836+
if (do_compress() && offset != 0 && Rd == x0 && is_imm_in_range(offset, 11, 1)) { \
28382837
c_j(offset); \
28392838
return; \
28402839
} \
@@ -2846,10 +2845,10 @@ enum Nf {
28462845
#undef INSN
28472846

28482847
// --------------------------
2849-
// jalr -> c.jr/c.jalr
28502848
#define INSN(NAME) \
28512849
void NAME(Register Rd, Register Rs, const int32_t offset) { \
2852-
if (check_rvc() && (offset == 0 && Rs != x0)) { \
2850+
/* jalr -> c.jr/c.jalr */ \
2851+
if (do_compress() && (offset == 0 && Rs != x0)) { \
28532852
if (Rd == x1) { \
28542853
c_jalr(Rs); \
28552854
return; \
@@ -2868,10 +2867,10 @@ enum Nf {
28682867
// --------------------------
28692868
// Miscellaneous Instructions
28702869
// --------------------------
2871-
// ebreak -> c.ebreak
28722870
#define INSN(NAME) \
28732871
void NAME() { \
2874-
if (check_rvc()) { \
2872+
/* ebreak -> c.ebreak */ \
2873+
if (do_compress()) { \
28752874
c_ebreak(); \
28762875
return; \
28772876
} \
@@ -2885,10 +2884,10 @@ enum Nf {
28852884
// --------------------------
28862885
// Immediate Instructions
28872886
// --------------------------
2888-
// li -> c.li
28892887
#define INSN(NAME) \
28902888
void NAME(Register Rd, int64_t imm) { \
2891-
if (check_rvc() && (is_imm_in_range(imm, 6, 0) && Rd != x0)) { \
2889+
/* li -> c.li */ \
2890+
if (do_compress() && (is_imm_in_range(imm, 6, 0) && Rd != x0)) { \
28922891
c_li(Rd, imm); \
28932892
return; \
28942893
} \
@@ -2899,10 +2898,11 @@ enum Nf {
28992898

29002899
#undef INSN
29012900

2902-
// addi -> c.addi/c.nop/c.mv/c.addi16sp/c.addi4spn.
2901+
// --------------------------
29032902
#define INSN(NAME) \
29042903
void NAME(Register Rd, Register Rs1, int32_t imm) { \
2905-
if (check_rvc()) { \
2904+
/* addi -> c.addi/c.nop/c.mv/c.addi16sp/c.addi4spn */ \
2905+
if (do_compress()) { \
29062906
if (Rd == Rs1 && is_imm_in_range(imm, 6, 0)) { \
29072907
c_addi(Rd, imm); \
29082908
return; \
@@ -2927,10 +2927,10 @@ enum Nf {
29272927
#undef INSN
29282928

29292929
// --------------------------
2930-
// addiw -> c.addiw
29312930
#define INSN(NAME) \
29322931
void NAME(Register Rd, Register Rs1, int32_t imm) { \
2933-
if (check_rvc() && (Rd == Rs1 && Rd != x0 && is_imm_in_range(imm, 6, 0))) { \
2932+
/* addiw -> c.addiw */ \
2933+
if (do_compress() && (Rd == Rs1 && Rd != x0 && is_imm_in_range(imm, 6, 0))) { \
29342934
c_addiw(Rd, imm); \
29352935
return; \
29362936
} \
@@ -2942,10 +2942,10 @@ enum Nf {
29422942
#undef INSN
29432943

29442944
// --------------------------
2945-
// and_imm12 -> c.andi
29462945
#define INSN(NAME) \
29472946
void NAME(Register Rd, Register Rs1, int32_t imm) { \
2948-
if (check_rvc() && \
2947+
/* and_imm12 -> c.andi */ \
2948+
if (do_compress() && \
29492949
(Rd == Rs1 && Rd->is_compressed_valid() && is_imm_in_range(imm, 6, 0))) { \
29502950
c_andi(Rd, imm); \
29512951
return; \
@@ -2960,10 +2960,10 @@ enum Nf {
29602960
// --------------------------
29612961
// Shift Immediate Instructions
29622962
// --------------------------
2963-
// slli -> c.slli
29642963
#define INSN(NAME) \
29652964
void NAME(Register Rd, Register Rs1, unsigned shamt) { \
2966-
if (check_rvc() && (Rd == Rs1 && Rd != x0 && shamt != 0)) { \
2965+
/* slli -> c.slli */ \
2966+
if (do_compress() && (Rd == Rs1 && Rd != x0 && shamt != 0)) { \
29672967
c_slli(Rd, shamt); \
29682968
return; \
29692969
} \
@@ -2975,10 +2975,10 @@ enum Nf {
29752975
#undef INSN
29762976

29772977
// --------------------------
2978-
// srai/srli -> c.srai/c.srli
29792978
#define INSN(NAME, C_NAME, NORMAL_NAME) \
29802979
void NAME(Register Rd, Register Rs1, unsigned shamt) { \
2981-
if (check_rvc() && (Rd == Rs1 && Rd->is_compressed_valid() && shamt != 0)) { \
2980+
/* srai/srli -> c.srai/c.srli */ \
2981+
if (do_compress() && (Rd == Rs1 && Rd->is_compressed_valid() && shamt != 0)) { \
29822982
C_NAME(Rd, shamt); \
29832983
return; \
29842984
} \
@@ -2993,10 +2993,10 @@ enum Nf {
29932993
// --------------------------
29942994
// Upper Immediate Instruction
29952995
// --------------------------
2996-
// lui -> c.lui
29972996
#define INSN(NAME) \
29982997
void NAME(Register Rd, int32_t imm) { \
2999-
if (check_rvc() && (Rd != x0 && Rd != x2 && imm != 0 && is_imm_in_range(imm, 18, 0))) { \
2998+
/* lui -> c.lui */ \
2999+
if (do_compress() && (Rd != x0 && Rd != x2 && imm != 0 && is_imm_in_range(imm, 18, 0))) { \
30003000
c_lui(Rd, imm); \
30013001
return; \
30023002
} \
@@ -3009,7 +3009,8 @@ enum Nf {
30093009

30103010
#define INSN(NAME) \
30113011
void NAME() { \
3012-
if (check_rvc()) { \
3012+
/* The illegal instruction in RVC is presented by a 16-bit 0. */ \
3013+
if (do_compress()) { \
30133014
emit_int16(0); \
30143015
return; \
30153016
} \

‎src/hotspot/cpu/riscv/globals_riscv.hpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,6 @@ define_pd_global(intx, InlineSmallCode, 1000);
9292
"Avoid generating unaligned memory accesses") \
9393
product(bool, UseRVV, false, EXPERIMENTAL, "Use RVV instructions") \
9494
product(bool, UseRVB, false, EXPERIMENTAL, "Use RVB instructions") \
95-
product(bool, UseRVC, false, EXPERIMENTAL, "Use RVC instructions") \
95+
product(bool, UseRVC, false, EXPERIMENTAL, "Use RVC instructions")
9696

9797
#endif // CPU_RISCV_GLOBALS_RISCV_HPP

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