8278833: riscv: Remove the x3 and x4 register saving logic in register savers

Reviewed-by: yadongwang, fjiang, fyang

Author: zhengxiaolinX

src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp

@@ -237,7 +237,7 @@ const int float_regs_as_doubles_size_in_slots = pd_nof_fpu_regs_frame_map * 2;
 //
 
 enum reg_save_layout {
-  reg_save_frame_size = 32 /* float */ + 32 /* integer */
+  reg_save_frame_size = 32 /* float */ + 30 /* integer excluding x3, x4 */
 };
 
 // Save off registers which might be killed by calls into the runtime.
@@ -262,7 +262,7 @@ static OopMap* generate_oop_map(StubAssembler* sasm, bool save_fpu_registers) {
   // in c1_FrameMap_riscv.cpp for detail.
   const static Register caller_save_cpu_regs[FrameMap::max_nof_caller_save_cpu_regs] = {x7, x10, x11, x12,
                                                                                         x13, x14, x15, x16, x17,
-                                                                                        x28,  x29, x30, x31};
+                                                                                        x28, x29, x30, x31};
   for (int i = 0; i < FrameMap::max_nof_caller_save_cpu_regs; i++) {
     Register r = caller_save_cpu_regs[i];
     int sp_offset = cpu_reg_save_offsets[r->encoding()];
@@ -286,8 +286,8 @@ static OopMap* save_live_registers(StubAssembler* sasm,
                                    bool save_fpu_registers = true) {
   __ block_comment("save_live_registers");
 
-  // if the number of pushed regs is odd, zr will be added
-  __ push_reg(RegSet::range(x3, x31), sp);    // integer registers except ra(x1) & sp(x2)
+  // if the number of pushed regs is odd, one slot will be reserved for alignment
+  __ push_reg(RegSet::range(x5, x31), sp);    // integer registers except ra(x1) & sp(x2) & gp(x3) & tp(x4)
 
   if (save_fpu_registers) {
     // float registers
@@ -296,7 +296,7 @@ static OopMap* save_live_registers(StubAssembler* sasm,
       __ fsd(as_FloatRegister(i), Address(sp, i * wordSize));
     }
   } else {
-    // we define reg_save_layout = 64 as the fixed frame size,
+    // we define reg_save_layout = 62 as the fixed frame size,
     // we should also sub 32 * wordSize to sp when save_fpu_registers == false
     __ addi(sp, sp, -32 * wordSize);
   }
@@ -316,8 +316,8 @@ static void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registe
     __ addi(sp, sp, 32 * wordSize);
   }
 
-  // if the number of popped regs is odd, zr will be added
-  __ pop_reg(RegSet::range(x3, x31), sp);   // integer registers except ra(x1) & sp(x2)
+  // if the number of popped regs is odd, the reserved slot for alignment will be removed
+  __ pop_reg(RegSet::range(x5, x31), sp);   // integer registers except ra(x1) & sp(x2) & gp(x3) & tp(x4)
 }
 
 static void restore_live_registers_except_r10(StubAssembler* sasm, bool restore_fpu_registers = true) {
@@ -332,10 +332,10 @@ static void restore_live_registers_except_r10(StubAssembler* sasm, bool restore_
     __ addi(sp, sp, 32 * wordSize);
   }
 
-  // if the number of popped regs is odd, zr will be added
-  // integer registers except ra(x1) & sp(x2) & x10
-  __ pop_reg(RegSet::range(x3, x9), sp);   // pop zr, x3 ~ x9
-  __ pop_reg(RegSet::range(x11, x31), sp); // pop x10 ~ x31, x10 will be loaded to zr
+  // pop integer registers except ra(x1) & sp(x2) & gp(x3) & tp(x4) & x10
+  // there is one reserved slot for alignment on the stack in save_live_registers().
+  __ pop_reg(RegSet::range(x5, x9), sp);   // pop x5 ~ x9 with the reserved slot for alignment
+  __ pop_reg(RegSet::range(x11, x31), sp); // pop x11 ~ x31; x10 will be automatically skipped here
 }
 
 void Runtime1::initialize_pd() {
@@ -349,11 +349,10 @@ void Runtime1::initialize_pd() {
     sp_offset += step;
   }
 
-  // we save x0, x3 ~ x31, except x1, x2
-  cpu_reg_save_offsets[0] = sp_offset;
+  // a slot reserved for stack 16-byte alignment, see MacroAssembler::push_reg
   sp_offset += step;
-  // 3: loop starts from x3
-  for (i = 3; i < FrameMap::nof_cpu_regs; i++) {
+  // we save x5 ~ x31, except x0 ~ x4: loop starts from x5
+  for (i = 5; i < FrameMap::nof_cpu_regs; i++) {
     cpu_reg_save_offsets[i] = sp_offset;
     sp_offset += step;
   }

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp

@@ -1118,18 +1118,19 @@ void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) {
   pop_reg(RegSet::of(x7) + RegSet::range(x10, x17) + RegSet::range(x28, x31) - exclude, sp);
 }
 
-// Push all the integer registers, except zr(x0) & sp(x2).
+// Push all the integer registers, except zr(x0) & sp(x2) & gp(x3) & tp(x4).
 void MacroAssembler::pusha() {
-  push_reg(0xfffffffa, sp);
+  push_reg(0xffffffe2, sp);
 }
 
+// Pop all the integer registers, except zr(x0) & sp(x2) & gp(x3) & tp(x4).
 void MacroAssembler::popa() {
-  pop_reg(0xfffffffa, sp);
+  pop_reg(0xffffffe2, sp);
 }
 
 void MacroAssembler::push_CPU_state(bool save_vectors, int vector_size_in_bytes) {
-  // integer registers, except zr(x0) & ra(x1) & sp(x2)
-  push_reg(0xfffffff8, sp);
+  // integer registers, except zr(x0) & ra(x1) & sp(x2) & gp(x3) & tp(x4)
+  push_reg(0xffffffe0, sp);
 
   // float registers
   addi(sp, sp, - 32 * wordSize);
@@ -1164,8 +1165,8 @@ void MacroAssembler::pop_CPU_state(bool restore_vectors, int vector_size_in_byte
   }
   addi(sp, sp, 32 * wordSize);
 
-  // integer registers, except zr(x0) & ra(x1) & sp(x2)
-  pop_reg(0xfffffff8, sp);
+  // integer registers, except zr(x0) & ra(x1) & sp(x2) & gp(x3) & tp(x4)
+  pop_reg(0xffffffe0, sp);
 }
 
 static int patch_offset_in_jal(address branch, int64_t offset) {

src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp

@@ -90,7 +90,7 @@ class RegisterSaver {
   // Offsets into the register save area
   // Used by deoptimization when it is managing result register
   // values on its own
-  // gregs:30, float_register:32; except: x1(ra) & x2(sp)
+  // gregs:28, float_register:32; except: x1(ra) & x2(sp) & gp(x3) & tp(x4)
   // |---v0---|<---SP
   // |---v1---|save vectors only in generate_handler_blob
   // |-- .. --|
@@ -99,9 +99,9 @@ class RegisterSaver {
   // |---f1---|
   // |   ..   |
   // |---f31--|
-  // |---zr---|
-  // |---x3---|
-  // |   x4   |
+  // |---reserved slot for stack alignment---|
+  // |---x5---|
+  // |   x6   |
   // |---.. --|
   // |---x31--|
   // |---fp---|
@@ -117,25 +117,25 @@ class RegisterSaver {
 #endif
     return f0_offset;
   }
-  int x0_offset_in_bytes(void) {
+  int reserved_slot_offset_in_bytes(void) {
     return f0_offset_in_bytes() +
            FloatRegisterImpl::max_slots_per_register *
            FloatRegisterImpl::number_of_registers *
            BytesPerInt;
   }
 
   int reg_offset_in_bytes(Register r) {
-    assert (r->encoding() > 2, "ra and sp not saved");
-    return x0_offset_in_bytes() + (r->encoding() - 2 /* x1, x2*/) * wordSize;
+    assert (r->encoding() > 4, "ra, sp, gp and tp not saved");
+    return reserved_slot_offset_in_bytes() + (r->encoding() - 4 /* x1, x2, x3, x4 */) * wordSize;
   }
 
   int freg_offset_in_bytes(FloatRegister f) {
     return f0_offset_in_bytes() + f->encoding() * wordSize;
   }
 
   int ra_offset_in_bytes(void) {
-    return x0_offset_in_bytes() +
-           (RegisterImpl::number_of_registers - 1) *
+    return reserved_slot_offset_in_bytes() +
+           (RegisterImpl::number_of_registers - 3) *
            RegisterImpl::max_slots_per_register *
            BytesPerInt;
   }
@@ -190,12 +190,14 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_
     oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset_in_slots), r->as_VMReg());
   }
 
-  // ignore zr, ra and sp, being ignored also by push_CPU_state (pushing zr only for stack alignment)
-  sp_offset_in_slots += RegisterImpl::max_slots_per_register;
   step_in_slots = RegisterImpl::max_slots_per_register;
-  for (int i = 3; i < RegisterImpl::number_of_registers; i++, sp_offset_in_slots += step_in_slots) {
+  // skip the slot reserved for alignment, see MacroAssembler::push_reg;
+  // also skip x5 ~ x6 on the stack because they are caller-saved registers.
+  sp_offset_in_slots += RegisterImpl::max_slots_per_register * 3;
+  // besides, we ignore x0 ~ x4 because push_CPU_state won't push them on the stack.
+  for (int i = 7; i < RegisterImpl::number_of_registers; i++, sp_offset_in_slots += step_in_slots) {
     Register r = as_Register(i);
-    if (r != xthread && r != t0 && r != t1) {
+    if (r != xthread) {
       oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset_in_slots + additional_frame_slots), r->as_VMReg());
     }
   }