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Commit 8703f14

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author
Jatin Bhateja
committed
8273322: Enhance macro logic optimization for masked logic operations.
Reviewed-by: kvn, sviswanathan
1 parent bc12381 commit 8703f14

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12 files changed

+1413
-51
lines changed

12 files changed

+1413
-51
lines changed

‎src/hotspot/cpu/x86/assembler_x86.cpp‎

Lines changed: 63 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it
@@ -9725,6 +9725,68 @@ void Assembler::evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, Addre
97259725
emit_operand(dst, src);
97269726
}
97279727

9728+
void Assembler::evpternlogd(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, XMMRegister src3, bool merge, int vector_len) {
9729+
assert(VM_Version::supports_evex(), "requires EVEX support");
9730+
assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
9731+
InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9732+
attributes.set_is_evex_instruction();
9733+
attributes.set_embedded_opmask_register_specifier(mask);
9734+
if (merge) {
9735+
attributes.reset_is_clear_context();
9736+
}
9737+
int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
9738+
emit_int24(0x25, (unsigned char)(0xC0 | encode), imm8);
9739+
}
9740+
9741+
void Assembler::evpternlogd(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len) {
9742+
assert(VM_Version::supports_evex(), "requires EVEX support");
9743+
assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
9744+
assert(dst != xnoreg, "sanity");
9745+
InstructionMark im(this);
9746+
InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9747+
attributes.set_is_evex_instruction();
9748+
attributes.set_embedded_opmask_register_specifier(mask);
9749+
attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
9750+
if (merge) {
9751+
attributes.reset_is_clear_context();
9752+
}
9753+
vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
9754+
emit_int8(0x25);
9755+
emit_operand(dst, src3);
9756+
emit_int8(imm8);
9757+
}
9758+
9759+
void Assembler::evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, XMMRegister src3, bool merge, int vector_len) {
9760+
assert(VM_Version::supports_evex(), "requires EVEX support");
9761+
assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
9762+
InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9763+
attributes.set_is_evex_instruction();
9764+
attributes.set_embedded_opmask_register_specifier(mask);
9765+
if (merge) {
9766+
attributes.reset_is_clear_context();
9767+
}
9768+
int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
9769+
emit_int24(0x25, (unsigned char)(0xC0 | encode), imm8);
9770+
}
9771+
9772+
void Assembler::evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len) {
9773+
assert(VM_Version::supports_evex(), "requires EVEX support");
9774+
assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
9775+
assert(dst != xnoreg, "sanity");
9776+
InstructionMark im(this);
9777+
InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9778+
attributes.set_is_evex_instruction();
9779+
attributes.set_embedded_opmask_register_specifier(mask);
9780+
attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
9781+
if (merge) {
9782+
attributes.reset_is_clear_context();
9783+
}
9784+
vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
9785+
emit_int8(0x25);
9786+
emit_operand(dst, src3);
9787+
emit_int8(imm8);
9788+
}
9789+
97289790
// duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
97299791
void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
97309792
assert(UseAVX >= 2, "");

‎src/hotspot/cpu/x86/assembler_x86.hpp‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it
@@ -2413,6 +2413,12 @@ class Assembler : public AbstractAssembler {
24132413
void evprorvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
24142414
void evprorvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
24152415

2416+
void evpternlogd(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, XMMRegister src3, bool merge, int vector_len);
2417+
void evpternlogd(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len);
2418+
void evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, XMMRegister src3, bool merge, int vector_len);
2419+
void evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len);
2420+
2421+
24162422
// Sub packed integers
24172423
void psubb(XMMRegister dst, XMMRegister src);
24182424
void psubw(XMMRegister dst, XMMRegister src);

‎src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp‎

Lines changed: 21 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 2020, 2022, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it
@@ -4152,6 +4152,26 @@ void C2_MacroAssembler::vector_castF2I_evex(XMMRegister dst, XMMRegister src, XM
41524152
bind(done);
41534153
}
41544154

4155+
void C2_MacroAssembler::evpternlog(XMMRegister dst, int func, KRegister mask, XMMRegister src2, XMMRegister src3,
4156+
bool merge, BasicType bt, int vlen_enc) {
4157+
if (bt == T_INT) {
4158+
evpternlogd(dst, func, mask, src2, src3, merge, vlen_enc);
4159+
} else {
4160+
assert(bt == T_LONG, "");
4161+
evpternlogq(dst, func, mask, src2, src3, merge, vlen_enc);
4162+
}
4163+
}
4164+
4165+
void C2_MacroAssembler::evpternlog(XMMRegister dst, int func, KRegister mask, XMMRegister src2, Address src3,
4166+
bool merge, BasicType bt, int vlen_enc) {
4167+
if (bt == T_INT) {
4168+
evpternlogd(dst, func, mask, src2, src3, merge, vlen_enc);
4169+
} else {
4170+
assert(bt == T_LONG, "");
4171+
evpternlogq(dst, func, mask, src2, src3, merge, vlen_enc);
4172+
}
4173+
}
4174+
41554175
#ifdef _LP64
41564176
void C2_MacroAssembler::vector_long_to_maskvec(XMMRegister dst, Register src, Register rtmp1,
41574177
Register rtmp2, XMMRegister xtmp, int mask_len,

‎src/hotspot/cpu/x86/c2_MacroAssembler_x86.hpp‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 2020, 2022, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it
@@ -311,4 +311,11 @@
311311
void vector_castD2L_evex(XMMRegister dst, XMMRegister src, XMMRegister xtmp1, XMMRegister xtmp2,
312312
KRegister ktmp1, KRegister ktmp2, AddressLiteral double_sign_flip,
313313
Register scratch, int vec_enc);
314+
315+
void evpternlog(XMMRegister dst, int func, KRegister mask, XMMRegister src2, XMMRegister src3,
316+
bool merge, BasicType bt, int vlen_enc);
317+
318+
void evpternlog(XMMRegister dst, int func, KRegister mask, XMMRegister src2, Address src3,
319+
bool merge, BasicType bt, int vlen_enc);
320+
314321
#endif // CPU_X86_C2_MACROASSEMBLER_X86_HPP

‎src/hotspot/cpu/x86/x86.ad‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1888,6 +1888,12 @@ const bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, Bas
18881888
case Op_FmaVD:
18891889
return true;
18901890

1891+
case Op_MacroLogicV:
1892+
if(bt != T_INT && bt != T_LONG) {
1893+
return false;
1894+
}
1895+
return true;
1896+
18911897
// Binary masked operations
18921898
case Op_AddVB:
18931899
case Op_AddVS:
@@ -9560,6 +9566,29 @@ instruct mask_opers_evex(kReg dst, kReg src1, kReg src2, kReg kscratch) %{
95609566
ins_pipe( pipe_slow );
95619567
%}
95629568

9569+
instruct vternlog_reg_masked(vec dst, vec src2, vec src3, immU8 func, kReg mask) %{
9570+
match(Set dst (MacroLogicV dst (Binary src2 (Binary src3 (Binary func mask)))));
9571+
format %{ "vternlog_masked $dst,$src2,$src3,$func,$mask\t! vternlog masked operation" %}
9572+
ins_encode %{
9573+
int vlen_enc = vector_length_encoding(this);
9574+
BasicType bt = Matcher::vector_element_basic_type(this);
9575+
__ evpternlog($dst$$XMMRegister, $func$$constant, $mask$$KRegister,
9576+
$src2$$XMMRegister, $src3$$XMMRegister, true, bt, vlen_enc);
9577+
%}
9578+
ins_pipe( pipe_slow );
9579+
%}
9580+
9581+
instruct vternlogd_mem_masked(vec dst, vec src2, memory src3, immU8 func, kReg mask) %{
9582+
match(Set dst (MacroLogicV dst (Binary src2 (Binary src3 (Binary func mask)))));
9583+
format %{ "vternlog_masked $dst,$src2,$src3,$func,$mask\t! vternlog masked operation" %}
9584+
ins_encode %{
9585+
int vlen_enc = vector_length_encoding(this);
9586+
BasicType bt = Matcher::vector_element_basic_type(this);
9587+
__ evpternlog($dst$$XMMRegister, $func$$constant, $mask$$KRegister,
9588+
$src2$$XMMRegister, $src3$$Address, true, bt, vlen_enc);
9589+
%}
9590+
ins_pipe( pipe_slow );
9591+
%}
95639592

95649593
instruct castMM(kReg dst)
95659594
%{

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