Enable RVC instructions (based on the basic patch)

Author: zhengxiaolinX

src/hotspot/cpu/riscv/assembler_riscv.cpp

@@ -80,6 +80,11 @@ void Assembler::subw(Register Rd, Register Rn, int64_t decrement, Register temp)
 }
 
 void Assembler::li(Register Rd, int64_t imm) {
+  CHECK_CEXT_AND_COMPRESSIBLE(is_imm_in_range(imm, 6, 0) && Rd != x0) {
+    c_li(Rd, imm);
+    return;
+  }
+
   // int64_t is in range 0x8000 0000 0000 0000 ~ 0x7fff ffff ffff ffff
   int shift = 12;
   int64_t upper = imm, lower = imm;

src/hotspot/cpu/riscv/assembler_riscv.hpp

@@ -1322,7 +1322,12 @@ void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Op
   }
 }
 
-void LIR_Assembler::align_call(LIR_Code code) {  }
+void LIR_Assembler::align_call(LIR_Code code) {
+  // C-Ext: With C-Ext a call may get 2-byte aligned.
+  //   the address of jal itself (which will be patched later) should not span the cache line.
+  //   See CallDynamicJavaDirectNode::compute_padding() for more info.
+  __ align(4);
+}
 
 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
   address call = __ trampoline_call(Address(op->addr(), rtype));

src/hotspot/cpu/riscv/assembler_riscv_c.hpp

@@ -46,7 +46,7 @@ define_pd_global(intx, OnStackReplacePercentage,     140);
 define_pd_global(intx, ConditionalMoveLimit,         0);
 define_pd_global(intx, FreqInlineSize,               325);
 define_pd_global(intx, MinJumpTableSize,             10);
-define_pd_global(intx, InteriorEntryAlignment,       16);
+define_pd_global(intx, InteriorEntryAlignment,       4);
 define_pd_global(intx, NewSizeThreadIncrease, ScaleForWordSize(4*K));
 define_pd_global(intx, LoopUnrollLimit,              60);
 define_pd_global(intx, LoopPercentProfileLimit,      10);

src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp

@@ -231,13 +231,19 @@ void BarrierSetAssembler::incr_allocated_bytes(MacroAssembler* masm,
   __ sd(tmp1, Address(xthread, in_bytes(JavaThread::allocated_bytes_offset())));
 }
 
+extern int nmethod_barrier_guard_offset();
+
 void BarrierSetAssembler::nmethod_entry_barrier(MacroAssembler* masm) {
   BarrierSetNMethod* bs_nm = BarrierSet::barrier_set()->barrier_set_nmethod();
 
   if (bs_nm == NULL) {
     return;
   }
 
+  // C-Ext: RISCV's amoswap instructions need an alignment for the memory address it swaps
+  //   when we reach here we may get a 2-byte alignment so need to align it
+  __ align(4, nmethod_barrier_guard_offset());
+
   Label skip, guard;
   Address thread_disarmed_addr(xthread, in_bytes(bs_nm->thread_disarmed_offset()));
 
@@ -256,6 +262,7 @@ void BarrierSetAssembler::nmethod_entry_barrier(MacroAssembler* masm) {
 
   __ bind(guard);
 
+  assert(__ offset() % 4 == 0, "RISCV CAS needs an alignment for memory");
   __ emit_int32(0); // nmethod guard value. Skipped over in common case.
 
   __ bind(skip);

src/hotspot/cpu/riscv/c2_globals_riscv.hpp

@@ -36,11 +36,18 @@
 #include "utilities/debug.hpp"
 
 class NativeNMethodBarrier: public NativeInstruction {
+public:
+  enum {
+    guard_offset   = 12 * instruction_size,
+    barrier_size   = guard_offset + 4,  // guard_offset + an int32 nmethod guard value
+  };
+
+private:
   address instruction_address() const { return addr_at(0); }
 
   int *guard_addr() {
     /* auipc + lwu + fence + lwu + beq + lui + addi + slli + addi + slli + jalr + j */
-    return reinterpret_cast<int*>(instruction_address() + 12 * 4);
+    return reinterpret_cast<int*>(instruction_address() + guard_offset);
   }
 
 public:
@@ -55,6 +62,10 @@ class NativeNMethodBarrier: public NativeInstruction {
   void verify() const;
 };
 
+int nmethod_barrier_guard_offset() {
+  return NativeNMethodBarrier::guard_offset;
+}
+
 // Store the instruction bitmask, bits and name for checking the barrier.
 struct CheckInsn {
   uint32_t mask;
@@ -141,7 +152,7 @@ void BarrierSetNMethod::deoptimize(nmethod* nm, address* return_address_ptr) {
 
 // see BarrierSetAssembler::nmethod_entry_barrier
 // auipc + lwu + fence + lwu + beq + movptr_with_offset(5 instructions) + jalr + j + int32
-static const int entry_barrier_offset = -4 * 13;
+static const int entry_barrier_offset = - NativeNMethodBarrier::barrier_size;
 
 static NativeNMethodBarrier* native_nmethod_barrier(nmethod* nm) {
   address barrier_address = nm->code_begin() + nm->frame_complete_offset() + entry_barrier_offset;

src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.cpp

@@ -37,7 +37,7 @@ define_pd_global(bool, TrapBasedNullChecks,      false);
 define_pd_global(bool, UncommonNullCast,         true);  // Uncommon-trap NULLs past to check cast
 
 define_pd_global(uintx, CodeCacheSegmentSize,    64 COMPILER1_AND_COMPILER2_PRESENT(+64)); // Tiered compilation has large code-entry alignment.
-define_pd_global(intx, CodeEntryAlignment,       64);
+define_pd_global(intx, CodeEntryAlignment,       16);
 define_pd_global(intx, OptoLoopAlignment,        16);
 
 #define DEFAULT_STACK_YELLOW_PAGES (2)

src/hotspot/cpu/riscv/gc/shared/barrierSetNMethod_riscv.cpp

@@ -88,8 +88,9 @@ static void pass_arg3(MacroAssembler* masm, Register arg) {
   }
 }
 
-void MacroAssembler::align(int modulus) {
-  while (offset() % modulus != 0) { nop(); }
+void MacroAssembler::align(int modulus, int extra_offset) {
+  CompressibleRegion cr(this);
+  while ((offset() + extra_offset) % modulus != 0) { nop(); }
 }
 
 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
@@ -809,6 +810,7 @@ void MacroAssembler::la(Register Rd, Label &label) {
 
   INSN(beq, feq, bnez);
   INSN(bne, feq, beqz);
+
 #undef INSN
 
 
@@ -2920,7 +2922,8 @@ address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
 
   // make sure 4 byte aligned here, so that the destination address would be
   // 8 byte aligned after 3 intructions
-  while (offset() % wordSize == 0) { nop(); }
+  // C-Ext: when we reach here we may get a 2-byte alignment so need to align it
+  align(wordSize, NativeCallTrampolineStub::data_offset);
 
   relocate(trampoline_stub_Relocation::spec(code()->insts()->start() +
                                             insts_call_instruction_offset));
@@ -2935,6 +2938,7 @@ address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
   bind(target);
   assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
          "should be");
+  assert(offset() % wordSize == 0, "address loaded by ld must be 8-byte aligned under riscv64");
   emit_int64((intptr_t)dest);
 
   const address stub_start_addr = addr_at(stub_start_offset);

src/hotspot/cpu/riscv/globals_riscv.hpp

@@ -49,7 +49,7 @@ class MacroAssembler: public Assembler {
   void safepoint_ifence();
 
   // Alignment
-  void align(int modulus);
+  void align(int modulus, int extra_offset = 0);
 
   // Stack frame creation/removal
   void enter() {
@@ -444,11 +444,11 @@ class MacroAssembler: public Assembler {
   void fsflagsi(unsigned imm);
 
   void beqz(Register Rs, const address &dest);
+  void bnez(Register Rs, const address &dest);
   void blez(Register Rs, const address &dest);
   void bgez(Register Rs, const address &dest);
   void bltz(Register Rs, const address &dest);
   void bgtz(Register Rs, const address &dest);
-  void bnez(Register Rs, const address &dest);
   void la(Register Rd, Label &label);
   void la(Register Rd, const address &dest);
   void la(Register Rd, const Address &adr);