8279213: riscv: RVB: Add zero/sign extend instructions

Reviewed-by: fyang

Author: feilongjiang

src/hotspot/cpu/riscv/assembler_riscv.hpp

@@ -30,7 +30,7 @@
 #include "asm/register.hpp"
 #include "assembler_riscv.inline.hpp"
 
-#define registerSize 64
+#define XLEN 64
 
 // definitions of various symbolic names for machine registers
 
@@ -1257,6 +1257,7 @@ enum operand_size { int8, int16, int32, uint32, int64 };
   }
 
   #include "assembler_riscv_v.hpp"
+  #include "assembler_riscv_b.hpp"
 
   virtual ~Assembler() {}
 

src/hotspot/cpu/riscv/assembler_riscv_b.hpp

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2021, Huawei Technologies Co., Ltd. All rights reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+ * or visit www.oracle.com if you need additional information or have any
+ * questions.
+ *
+ */
+
+#ifndef CPU_RISCV_ASSEMBLER_RISCV_B_HPP
+#define CPU_RISCV_ASSEMBLER_RISCV_B_HPP
+
+#define INSN(NAME, op, funct3, funct7)                  \
+  void NAME(Register Rd, Register Rs1, Register Rs2) {  \
+    unsigned insn = 0;                                  \
+    patch((address)&insn, 6,  0, op);                   \
+    patch((address)&insn, 14, 12, funct3);              \
+    patch((address)&insn, 31, 25, funct7);              \
+    patch_reg((address)&insn, 7, Rd);                   \
+    patch_reg((address)&insn, 15, Rs1);                 \
+    patch_reg((address)&insn, 20, Rs2);                 \
+    emit(insn);                                         \
+  }
+
+  INSN(add_uw, 0b0111011, 0b000, 0b0000100);
+
+#undef INSN
+
+#define INSN(NAME, op, funct3, funct12)                 \
+  void NAME(Register Rd, Register Rs1) {                \
+    unsigned insn = 0;                                  \
+    patch((address)&insn, 6, 0, op);                    \
+    patch((address)&insn, 14, 12, funct3);              \
+    patch((address)&insn, 31, 20, funct12);             \
+    patch_reg((address)&insn, 7, Rd);                   \
+    patch_reg((address)&insn, 15, Rs1);                 \
+    emit(insn);                                         \
+  }
+
+  INSN(sext_b, 0b0010011, 0b001, 0b011000000100);
+  INSN(sext_h, 0b0010011, 0b001, 0b011000000101);
+  INSN(zext_h, 0b0111011, 0b100, 0b000010000000);
+
+#undef INSN
+
+// RVB pseudo instructions
+// zero extend word
+void zext_w(Register Rd, Register Rs) {
+  add_uw(Rd, Rs, zr);
+}
+
+
+#endif // CPU_RISCV_ASSEMBLER_RISCV_B_HPP

src/hotspot/cpu/riscv/c1_LIRAssembler_arith_riscv.cpp

@@ -64,8 +64,7 @@ void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right,
         if (is_imm_in_range(c - 1, 12, 0)) {
           __ andi(t1, t1, c - 1);
         } else {
-          __ slli(t1, t1, registerSize - shift);
-          __ srli(t1, t1, registerSize - shift);
+          __ zero_extend(t1, t1, shift);
         }
         __ subw(dreg, t1, t0);
       }
@@ -79,8 +78,7 @@ void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right,
         if (is_imm_in_range(c - 1, 12, 0)) {
           __ andi(t0, t0, c - 1);
         } else {
-          __ slli(t0, t0, registerSize - shift);
-          __ srli(t0, t0, registerSize - shift);
+          __ zero_extend(t0, t0, shift);
         }
         __ addw(dreg, t0, lreg);
         __ sraiw(dreg, dreg, shift);
@@ -203,8 +201,7 @@ void LIR_Assembler::arith_op_double_cpu(LIR_Code code, LIR_Opr left, LIR_Opr rig
           if (is_imm_in_range(c - 1, 12, 0)) {
             __ andi(t0, t0, c - 1);
           } else {
-            __ slli(t0, t0, registerSize - shift);
-            __ srli(t0, t0, registerSize - shift);
+            __ zero_extend(t0, t0, shift);
           }
           __ add(dreg, t0, lreg_lo);
           __ srai(dreg, dreg, shift);
@@ -223,8 +220,7 @@ void LIR_Assembler::arith_op_double_cpu(LIR_Code code, LIR_Opr left, LIR_Opr rig
           if (is_imm_in_range(c - 1, 12, 0)) {
             __ andi(t1, t1, c - 1);
           } else {
-            __ slli(t1, t1, registerSize - shift);
-            __ srli(t1, t1, registerSize - shift);
+            __ zero_extend(t1, t1, shift);
           }
           __ sub(dreg, t1, t0);
         }

src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp

@@ -951,13 +951,13 @@ void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
     case Bytecodes::_d2f:
       __ fcvt_s_d(dest->as_float_reg(), src->as_double_reg()); break;
     case Bytecodes::_i2c:
-      __ zero_ext(dest->as_register(), src->as_register(), registerSize - 16); break; // 16: char size
+      __ zero_extend(dest->as_register(), src->as_register(), 16); break;
     case Bytecodes::_i2l:
       __ addw(dest->as_register_lo(), src->as_register(), zr); break;
     case Bytecodes::_i2s:
-      __ sign_ext(dest->as_register(), src->as_register(), registerSize - 16); break; // 16: short size
+      __ sign_extend(dest->as_register(), src->as_register(), 16); break;
     case Bytecodes::_i2b:
-      __ sign_ext(dest->as_register(), src->as_register(), registerSize - 8); break;  // 8: byte size
+      __ sign_extend(dest->as_register(), src->as_register(), 8); break;
     case Bytecodes::_l2i:
       _masm->block_comment("FIXME: This coulde be no-op");
       __ addw(dest->as_register(), src->as_register_lo(), zr); break;

src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp

@@ -819,8 +819,8 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
           __ sll(arr_size, length, t0);
           int lh_header_size_width = log2i_exact(Klass::_lh_header_size_mask + 1);
           int lh_header_size_msb = Klass::_lh_header_size_shift + lh_header_size_width;
-          __ slli(tmp1, tmp1, registerSize - lh_header_size_msb);
-          __ srli(tmp1, tmp1, registerSize - lh_header_size_width);
+          __ slli(tmp1, tmp1, XLEN - lh_header_size_msb);
+          __ srli(tmp1, tmp1, XLEN - lh_header_size_width);
           __ add(arr_size, arr_size, tmp1);
           __ addi(arr_size, arr_size, MinObjAlignmentInBytesMask); // align up
           __ andi(arr_size, arr_size, ~(uint)MinObjAlignmentInBytesMask);

src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp

@@ -450,10 +450,10 @@ void C2_MacroAssembler::string_indexof(Register haystack, Register needle,
     // convert Latin1 to UTF. eg: 0x0000abcd -> 0x0a0b0c0d
     // We'll have to wait until load completed, but it's still faster than per-character loads+checks
     srli(tmp3, tmp6, BitsPerByte * (wordSize / 2 - needle_chr_size)); // pattern[m-1], eg:0x0000000a
-    slli(ch2, tmp6, registerSize - 24);
-    srli(ch2, ch2, registerSize - 8); // pattern[m-2], 0x0000000b
-    slli(ch1, tmp6, registerSize - 16);
-    srli(ch1, ch1, registerSize - 8); // pattern[m-3], 0x0000000c
+    slli(ch2, tmp6, XLEN - 24);
+    srli(ch2, ch2, XLEN - 8); // pattern[m-2], 0x0000000b
+    slli(ch1, tmp6, XLEN - 16);
+    srli(ch1, ch1, XLEN - 8); // pattern[m-3], 0x0000000c
     andi(tmp6, tmp6, 0xff); // pattern[m-4], 0x0000000d
     slli(ch2, ch2, 16);
     orr(ch2, ch2, ch1); // 0x00000b0c

src/hotspot/cpu/riscv/globals_riscv.hpp

@@ -90,6 +90,7 @@ define_pd_global(intx, InlineSmallCode,          1000);
           "Extend fence.i to fence.i + fence.")                                  \
   product(bool, AvoidUnalignedAccesses, true,                                    \
           "Avoid generating unaligned memory accesses")                          \
-  product(bool, UseRVV, false, EXPERIMENTAL, "Use RVV instructions")
+  product(bool, UseRVV, false, EXPERIMENTAL, "Use RVV instructions")             \
+  product(bool, UseRVB, false, EXPERIMENTAL, "Use RVB instructions")
 
 #endif // CPU_RISCV_GLOBALS_RISCV_HPP

src/hotspot/cpu/riscv/interp_masm_riscv.cpp

@@ -67,17 +67,17 @@ void InterpreterMacroAssembler::narrow(Register result) {
   bind(notBool);
   mv(t1, T_BYTE);
   bne(t0, t1, notByte);
-  sign_ext(result, result, registerSize - 8);
+  sign_extend(result, result, 8);
   j(done);
 
   bind(notByte);
   mv(t1, T_CHAR);
   bne(t0, t1, notChar);
-  zero_ext(result, result, registerSize - 16); // turncate upper 48 bits
+  zero_extend(result, result, 16);
   j(done);
 
   bind(notChar);
-  sign_ext(result, result, registerSize - 16); // sign-extend short
+  sign_extend(result, result, 16);
 
   // Nothing to do for T_INT
   bind(done);
@@ -250,8 +250,8 @@ void InterpreterMacroAssembler::get_cache_and_index_and_bytecode_at_bcp(Register
   lwu(bytecode, bytecode);
   membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
   const int shift_count = (1 + byte_no) * BitsPerByte;
-  slli(bytecode, bytecode, registerSize - (shift_count + BitsPerByte));
-  srli(bytecode, bytecode, registerSize - BitsPerByte);
+  slli(bytecode, bytecode, XLEN - (shift_count + BitsPerByte));
+  srli(bytecode, bytecode, XLEN - BitsPerByte);
 }
 
 void InterpreterMacroAssembler::get_cache_entry_pointer_at_bcp(Register cache,

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp

@@ -683,6 +683,10 @@ void MacroAssembler::sext_w(Register Rd, Register Rs) {
   addiw(Rd, Rs, 0);
 }
 
+void MacroAssembler::zext_b(Register Rd, Register Rs) {
+  andi(Rd, Rs, 0xFF);
+}
+
 void MacroAssembler::seqz(Register Rd, Register Rs) {
   sltiu(Rd, Rs, 1);
 }
@@ -1902,7 +1906,7 @@ void MacroAssembler::encode_klass_not_null(Register dst, Register src, Register
 
   if (((uint64_t)(uintptr_t)CompressedKlassPointers::base() & 0xffffffff) == 0 &&
       CompressedKlassPointers::shift() == 0) {
-    zero_ext(dst, src, 32); // clear upper 32 bits
+    zero_extend(dst, src, 32);
     return;
   }
 
@@ -2219,7 +2223,7 @@ void MacroAssembler::load_reserved(Register addr,
       break;
     case uint32:
       lr_w(t0, addr, acquire);
-      clear_upper_bits(t0, 32);
+      zero_extend(t0, t0, 32);
       break;
     default:
       ShouldNotReachHere();
@@ -2262,7 +2266,7 @@ void MacroAssembler::cmpxchg_narrow_value_helper(Register addr, Register expecte
   } else {
     // size == int16 case
     addi(mask, zr, -1);
-    zero_ext(mask, mask, registerSize - 16);
+    zero_extend(mask, mask, 16);
   }
   sll(mask, mask, shift);
 
@@ -2315,10 +2319,10 @@ void MacroAssembler::cmpxchg_narrow_value(Register addr, Register expected,
     srl(result, tmp, shift);
 
     if (size == int8) {
-      sign_ext(result, result, registerSize - 8);
+      sign_extend(result, result, 8);
     } else {
       // size == int16 case
-      sign_ext(result, result, registerSize - 16);
+      sign_extend(result, result, 16);
     }
   }
 }
@@ -2448,7 +2452,7 @@ ATOMIC_XCHG(xchgalw, amoswap_w, Assembler::aq, Assembler::rl)
 #define ATOMIC_XCHGU(OP1, OP2)                                                       \
 void MacroAssembler::atomic_##OP1(Register prev, Register newv, Register addr) {     \
   atomic_##OP2(prev, newv, addr);                                                    \
-  clear_upper_bits(prev, 32);                                                        \
+  zero_extend(prev, prev, 32);                                                       \
   return;                                                                            \
 }
 
@@ -2827,7 +2831,7 @@ void  MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
   RelocationHolder rspec = oop_Relocation::spec(oop_index);
   code_section()->relocate(inst_mark(), rspec);
   li32(dst, 0xDEADBEEF);
-  clear_upper_bits(dst, 32); // clear upper 32bit, do not sign extend.
+  zero_extend(dst, dst, 32);
 }
 
 void  MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
@@ -2841,7 +2845,7 @@ void  MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
   code_section()->relocate(inst_mark(), rspec);
   narrowKlass nk = CompressedKlassPointers::encode(k);
   li32(dst, nk);
-  clear_upper_bits(dst, 32); // clear upper 32bit, do not sign extend.
+  zero_extend(dst, dst, 32);
 }
 
 // Maybe emit a call via a trampoline.  If the code cache is small
@@ -3050,7 +3054,7 @@ void MacroAssembler::mul_add(Register out, Register in, Register offset,
   mv(tmp, out);
   mv(out, zr);
   beqz(len, L_end);
-  zero_ext(k, k, 32);
+  zero_extend(k, k, 32);
   slli(t0, offset, LogBytesPerInt);
   add(offset, tmp, t0);
   slli(t0, len, LogBytesPerInt);
@@ -3427,14 +3431,42 @@ void MacroAssembler::zero_memory(Register addr, Register len, Register tmp1) {
   bnez(len, loop);
 }
 
-void MacroAssembler::zero_ext(Register dst, Register src, int clear_bits) {
-  slli(dst, src, clear_bits);
-  srli(dst, dst, clear_bits);
+void MacroAssembler::zero_extend(Register dst, Register src, int bits) {
+  if (UseRVB) {
+    if (bits == 16) {
+      zext_h(dst, src);
+      return;
+    } else if (bits == 32) {
+      zext_w(dst, src);
+      return;
+    }
+  }
+
+  if (bits == 8) {
+    zext_b(dst, src);
+  } else {
+    slli(dst, src, XLEN - bits);
+    srli(dst, dst, XLEN - bits);
+  }
 }
 
-void MacroAssembler::sign_ext(Register dst, Register src, int clear_bits) {
-  slli(dst, src, clear_bits);
-  srai(dst, dst, clear_bits);
+void MacroAssembler::sign_extend(Register dst, Register src, int bits) {
+  if (UseRVB) {
+    if (bits == 8) {
+      sext_b(dst, src);
+      return;
+    } else if (bits == 16) {
+      sext_h(dst, src);
+      return;
+    }
+  }
+
+  if (bits == 32) {
+    sext_w(dst, src);
+  } else {
+    slli(dst, src, XLEN - bits);
+    srai(dst, dst, XLEN - bits);
+  }
 }
 
 void MacroAssembler::cmp_l2i(Register dst, Register src1, Register src2, Register tmp)