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feilongjiangRealFYang
feilongjiang
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RealFYang
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8279344: riscv: RVB: Add bitwise rotation instructions
Reviewed-by: fyang
1 parent e73db5d commit c1c0833

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6 files changed

+273
-25
lines changed

6 files changed

+273
-25
lines changed

‎make/hotspot/gensrc/GensrcAdlc.gmk‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
#
2-
# Copyright (c) 2013, 2021, Oracle and/or its affiliates. All rights reserved.
2+
# Copyright (c) 2013, 2022, Oracle and/or its affiliates. All rights reserved.
33
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
#
55
# This code is free software; you can redistribute it and/or modify it
@@ -149,6 +149,7 @@ ifeq ($(call check-jvm-feature, compiler2), true)
149149
ifeq ($(HOTSPOT_TARGET_CPU_ARCH), riscv)
150150
AD_SRC_FILES += $(call uniq, $(wildcard $(foreach d, $(AD_SRC_ROOTS), \
151151
$d/cpu/$(HOTSPOT_TARGET_CPU_ARCH)/$(HOTSPOT_TARGET_CPU_ARCH)_v.ad \
152+
$d/cpu/$(HOTSPOT_TARGET_CPU_ARCH)/$(HOTSPOT_TARGET_CPU_ARCH)_b.ad \
152153
)))
153154
endif
154155

‎src/hotspot/cpu/riscv/assembler_riscv_b.hpp‎

Lines changed: 39 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3-
* Copyright (c) 2021, Huawei Technologies Co., Ltd. All rights reserved.
3+
* Copyright (c) 2021, 2022, Huawei Technologies Co., Ltd. All rights reserved.
44
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
55
*
66
* This code is free software; you can redistribute it and/or modify it
@@ -39,6 +39,10 @@
3939
}
4040

4141
INSN(add_uw, 0b0111011, 0b000, 0b0000100);
42+
INSN(rol, 0b0110011, 0b001, 0b0110000);
43+
INSN(rolw, 0b0111011, 0b001, 0b0110000);
44+
INSN(ror, 0b0110011, 0b101, 0b0110000);
45+
INSN(rorw, 0b0111011, 0b101, 0b0110000);
4246

4347
#undef INSN
4448

@@ -59,6 +63,40 @@
5963

6064
#undef INSN
6165

66+
#define INSN(NAME, op, funct3, funct6) \
67+
void NAME(Register Rd, Register Rs1, unsigned shamt) {\
68+
guarantee(shamt <= 0x3f, "Shamt is invalid"); \
69+
unsigned insn = 0; \
70+
patch((address)&insn, 6, 0, op); \
71+
patch((address)&insn, 14, 12, funct3); \
72+
patch((address)&insn, 25, 20, shamt); \
73+
patch((address)&insn, 31, 26, funct6); \
74+
patch_reg((address)&insn, 7, Rd); \
75+
patch_reg((address)&insn, 15, Rs1); \
76+
emit(insn); \
77+
}
78+
79+
INSN(rori, 0b0010011, 0b101, 0b011000);
80+
81+
#undef INSN
82+
83+
#define INSN(NAME, op, funct3, funct7) \
84+
void NAME(Register Rd, Register Rs1, unsigned shamt){ \
85+
guarantee(shamt <= 0x1f, "Shamt is invalid"); \
86+
unsigned insn = 0; \
87+
patch((address)&insn, 6, 0, op); \
88+
patch((address)&insn, 14, 12, funct3); \
89+
patch((address)&insn, 24, 20, shamt); \
90+
patch((address)&insn, 31, 25, funct7); \
91+
patch_reg((address)&insn, 7, Rd); \
92+
patch_reg((address)&insn, 15, Rs1); \
93+
emit(insn); \
94+
}
95+
96+
INSN(roriw, 0b0011011, 0b101, 0b0110000);
97+
98+
#undef INSN
99+
62100
// RVB pseudo instructions
63101
// zero extend word
64102
void zext_w(Register Rd, Register Rs) {

‎src/hotspot/cpu/riscv/macroAssembler_riscv.cpp‎

Lines changed: 21 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
/*
22
* Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
33
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4-
* Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
4+
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
55
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
66
*
77
* This code is free software; you can redistribute it and/or modify it
@@ -3121,11 +3121,16 @@ void MacroAssembler::cadc(Register dst, Register src1, Register src2, Register c
31213121
}
31223122

31233123
// rotate right with shift bits
3124-
void MacroAssembler::ror(Register dst, Register src, uint32_t shift, Register tmp)
3124+
void MacroAssembler::ror_imm(Register dst, Register src, uint32_t shift, Register tmp)
31253125
{
3126+
if (UseRVB) {
3127+
rori(dst, src, shift);
3128+
return;
3129+
}
3130+
31263131
assert_different_registers(dst, tmp);
31273132
assert_different_registers(src, tmp);
3128-
assert(shift <= 64, "shift amount must be <= 64");
3133+
assert(shift < 64, "shift amount must be < 64");
31293134
slli(tmp, src, 64 - shift);
31303135
srli(dst, src, shift);
31313136
orr(dst, dst, tmp);
@@ -3207,7 +3212,7 @@ void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register
32073212
slli(t0, xstart, LogBytesPerInt);
32083213
add(t0, x, t0);
32093214
ld(x_xstart, Address(t0, 0));
3210-
ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
3215+
ror_imm(x_xstart, x_xstart, 32); // convert big-endian to little-endian
32113216

32123217
bind(L_first_loop);
32133218
subw(idx, idx, 1);
@@ -3218,7 +3223,7 @@ void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register
32183223
slli(t0, idx, LogBytesPerInt);
32193224
add(t0, y, t0);
32203225
ld(y_idx, Address(t0, 0));
3221-
ror(y_idx, y_idx, 32); // convert big-endian to little-endian
3226+
ror_imm(y_idx, y_idx, 32); // convert big-endian to little-endian
32223227
bind(L_multiply);
32233228

32243229
mulhu(t0, x_xstart, y_idx);
@@ -3227,7 +3232,7 @@ void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register
32273232
adc(carry, t0, zr, t1);
32283233

32293234
subw(kdx, kdx, 2);
3230-
ror(product, product, 32); // back to big-endian
3235+
ror_imm(product, product, 32); // back to big-endian
32313236
slli(t0, kdx, LogBytesPerInt);
32323237
add(t0, z, t0);
32333238
sd(product, Address(t0, 0));
@@ -3292,17 +3297,17 @@ void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
32923297
slli(t0, idx, LogBytesPerInt);
32933298
add(tmp6, z, t0);
32943299

3295-
ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
3296-
ror(yz_idx2, yz_idx2, 32);
3300+
ror_imm(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
3301+
ror_imm(yz_idx2, yz_idx2, 32);
32973302

32983303
ld(t1, Address(tmp6, 0));
32993304
ld(t0, Address(tmp6, wordSize));
33003305

33013306
mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
33023307
mulhu(tmp4, product_hi, yz_idx1);
33033308

3304-
ror(t0, t0, 32, tmp); // convert big-endian to little-endian
3305-
ror(t1, t1, 32, tmp);
3309+
ror_imm(t0, t0, 32, tmp); // convert big-endian to little-endian
3310+
ror_imm(t1, t1, 32, tmp);
33063311

33073312
mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp
33083313
mulhu(carry2, product_hi, yz_idx2);
@@ -3315,8 +3320,8 @@ void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
33153320
cad(tmp4, tmp4, t1, carry2);
33163321
adc(carry, carry, zr, carry2);
33173322

3318-
ror(tmp3, tmp3, 32); // convert little-endian to big-endian
3319-
ror(tmp4, tmp4, 32);
3323+
ror_imm(tmp3, tmp3, 32); // convert little-endian to big-endian
3324+
ror_imm(tmp4, tmp4, 32);
33203325
sd(tmp4, Address(tmp6, 0));
33213326
sd(tmp3, Address(tmp6, wordSize));
33223327

@@ -3334,19 +3339,19 @@ void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
33343339
slli(t0, idx, LogBytesPerInt);
33353340
add(t0, y, t0);
33363341
ld(yz_idx1, Address(t0, 0));
3337-
ror(yz_idx1, yz_idx1, 32);
3342+
ror_imm(yz_idx1, yz_idx1, 32);
33383343

33393344
mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
33403345
mulhu(tmp4, product_hi, yz_idx1);
33413346

33423347
slli(t0, idx, LogBytesPerInt);
33433348
add(t0, z, t0);
33443349
ld(yz_idx2, Address(t0, 0));
3345-
ror(yz_idx2, yz_idx2, 32, tmp);
3350+
ror_imm(yz_idx2, yz_idx2, 32, tmp);
33463351

33473352
add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2, tmp);
33483353

3349-
ror(tmp3, tmp3, 32, tmp);
3354+
ror_imm(tmp3, tmp3, 32, tmp);
33503355
sd(tmp3, Address(t0, 0));
33513356

33523357
bind(L_check_1);
@@ -3532,7 +3537,7 @@ void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Regi
35323537
slli(t0, xstart, LogBytesPerInt);
35333538
add(t0, x, t0);
35343539
ld(product_hi, Address(t0, 0));
3535-
ror(product_hi, product_hi, 32); // convert big-endian to little-endian
3540+
ror_imm(product_hi, product_hi, 32); // convert big-endian to little-endian
35363541

35373542
Label L_third_loop_prologue;
35383543
bind(L_third_loop_prologue);

‎src/hotspot/cpu/riscv/macroAssembler_riscv.hpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
/*
22
* Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
33
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4-
* Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
4+
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
55
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
66
*
77
* This code is free software; you can redistribute it and/or modify it
@@ -654,7 +654,7 @@ class MacroAssembler: public Assembler {
654654
void adc(Register dst, Register src1, Register src2, Register carry);
655655
void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
656656
Register src1, Register src2, Register carry);
657-
void ror(Register dst, Register src, uint32_t imm, Register tmp = t0);
657+
void ror_imm(Register dst, Register src, uint32_t shift, Register tmp = t0);
658658
void multiply_32_x_32_loop(Register x, Register xstart, Register x_xstart,
659659
Register y, Register y_idx, Register z,
660660
Register carry, Register product,

‎src/hotspot/cpu/riscv/riscv.ad‎

Lines changed: 32 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
//
22
// Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
33
// Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4-
// Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
4+
// Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
55
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
66
//
77
// This code is free software; you can redistribute it and/or modify it
@@ -2722,6 +2722,24 @@ operand immI_le_4()
27222722
interface(CONST_INTER);
27232723
%}
27242724

2725+
operand immI_16()
2726+
%{
2727+
predicate(n->get_int() == 16);
2728+
match(ConI);
2729+
op_cost(0);
2730+
format %{ %}
2731+
interface(CONST_INTER);
2732+
%}
2733+
2734+
operand immI_24()
2735+
%{
2736+
predicate(n->get_int() == 24);
2737+
match(ConI);
2738+
op_cost(0);
2739+
format %{ %}
2740+
interface(CONST_INTER);
2741+
%}
2742+
27252743
operand immI_31()
27262744
%{
27272745
predicate(n->get_int() == 31);
@@ -2854,6 +2872,16 @@ operand immByteMapBase()
28542872
interface(CONST_INTER);
28552873
%}
28562874

2875+
// Int Immediate: low 16-bit mask
2876+
operand immI_16bits()
2877+
%{
2878+
predicate(n->get_int() == 0xFFFF);
2879+
match(ConI);
2880+
op_cost(0);
2881+
format %{ %}
2882+
interface(CONST_INTER);
2883+
%}
2884+
28572885
// Long Immediate: low 32-bit mask
28582886
operand immL_32bits()
28592887
%{
@@ -7857,14 +7885,13 @@ instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
78577885
ins_pipe(ialu_reg);
78587886
%}
78597887

7860-
// unsigned int to long (Zero-extend)
7861-
// this pattern occurs in bigmath arithmetic
7862-
instruct convUI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
7888+
// int to unsigned long (Zero-extend)
7889+
instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
78637890
%{
78647891
match(Set dst (AndL (ConvI2L src) mask));
78657892

78667893
ins_cost(ALU_COST * 2);
7867-
format %{ "zero_extend $dst, $src, 32\t# ui2l, #@convUI2L_reg_reg" %}
7894+
format %{ "zero_extend $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
78687895

78697896
ins_encode %{
78707897
__ zero_extend(as_Register($dst$$reg), as_Register($src$$reg), 32);

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