RVC: basic instruction set

Author: zhengxiaolinX

src/hotspot/cpu/riscv/assembler_riscv.hpp

@@ -255,6 +255,7 @@ class InternalAddress: public Address {
 
 class Assembler : public AbstractAssembler {
 public:
+  #include "assembler_riscv_c.hpp"
 
   enum { instruction_size = 4 };
 
@@ -1238,7 +1239,7 @@ enum operand_size { int8, int16, int32, uint32, int64 };
   void sub(Register Rd, Register Rn, int64_t decrement, Register temp = t0);
   void subw(Register Rd, Register Rn, int64_t decrement, Register temp = t0);
 
-  Assembler(CodeBuffer* code) : AbstractAssembler(code) {
+  Assembler(CodeBuffer* code) : AbstractAssembler(code), _in_compressible_region(false) {
   }
 
   // Stack overflow checking
@@ -1263,6 +1264,4 @@ enum operand_size { int8, int16, int32, uint32, int64 };
 
 };
 
-class BiasedLockingCounters;
-
 #endif // CPU_RISCV_ASSEMBLER_RISCV_HPP

src/hotspot/cpu/riscv/assembler_riscv_c.hpp

@@ -91,6 +91,7 @@ define_pd_global(intx, InlineSmallCode,          1000);
   product(bool, AvoidUnalignedAccesses, true,                                    \
           "Avoid generating unaligned memory accesses")                          \
   product(bool, UseRVV, false, EXPERIMENTAL, "Use RVV instructions")             \
-  product(bool, UseRVB, false, EXPERIMENTAL, "Use RVB instructions")
+  product(bool, UseRVB, false, EXPERIMENTAL, "Use RVB instructions")             \
+  product(bool, UseRVC, false, EXPERIMENTAL, "Use RVC instructions")             \
 
 #endif // CPU_RISCV_GLOBALS_RISCV_HPP

src/hotspot/cpu/riscv/globals_riscv.hpp

@@ -1320,7 +1320,10 @@ int MacroAssembler::pd_patch_instruction_size(address branch, address target) {
     int64_t imm = (intptr_t)target;
     return patch_imm_in_li32(branch, (int32_t)imm);
   } else {
-    tty->print_cr("pd_patch_instruction_size: instruction 0x%x could not be patched!\n", *(unsigned*)branch);
+#ifdef ASSERT
+    tty->print_cr("pd_patch_instruction_size: instruction 0x%x at " INTPTR_FORMAT " could not be patched!\n", *(unsigned*)branch, p2i(branch));
+    Disassembler::decode(branch - 10, branch + 10);
+#endif
     ShouldNotReachHere();
   }
   return -1;

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp

@@ -53,7 +53,8 @@ class NativeInstruction {
   friend bool is_NativeCallTrampolineStub_at(address);
  public:
   enum {
-    instruction_size = 4
+    instruction_size = 4,
+    compressed_instruction_size = 2,
   };
 
   juint encoding() const {
@@ -422,10 +423,10 @@ inline NativeMovRegMem* nativeMovRegMem_at (address addr) {
 class NativeJump: public NativeInstruction {
  public:
   enum RISCV64_specific_constants {
-    instruction_size            =    4,
+    instruction_size            =    NativeInstruction::instruction_size,
     instruction_offset          =    0,
     data_offset                 =    0,
-    next_instruction_offset     =    4
+    next_instruction_offset     =    NativeInstruction::instruction_size
   };
 
   address instruction_address() const       { return addr_at(instruction_offset); }

src/hotspot/cpu/riscv/nativeInst_riscv.hpp

@@ -58,7 +58,11 @@ class RegisterImpl: public AbstractRegisterImpl {
   enum {
     number_of_registers      = 32,
     number_of_byte_registers = 32,
-    max_slots_per_register   = 2
+    max_slots_per_register   = 2,
+
+    // C-Ext: integer registers in the range of [x8~x15] are correspond for RVC. Please see Table 16.2 in spec.
+    compressed_register_base = 8,
+    compressed_register_top  = 15,
   };
 
   // derived registers, offsets, and addresses
@@ -71,10 +75,13 @@ class RegisterImpl: public AbstractRegisterImpl {
 
   // accessors
   int   encoding() const                         { assert(is_valid(), "invalid register"); return (intptr_t)this; }
+  int   compressed_encoding() const              { assert(is_compressed_valid(), "invalid compressed register"); return ((intptr_t)this - compressed_register_base); }
   bool  is_valid() const                         { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
+  bool  is_compressed_valid() const              { return compressed_register_base <= (intptr_t)this && (intptr_t)this <= compressed_register_top; }
   bool  has_byte_register() const                { return 0 <= (intptr_t)this && (intptr_t)this < number_of_byte_registers; }
   const char* name() const;
   int   encoding_nocheck() const                 { return (intptr_t)this; }
+  int   compressed_encoding_nocheck() const      { return ((intptr_t)this - compressed_register_base); }
 
   // Return the bit which represents this register.  This is intended
   // to be ORed into a bitmask: for usage see class RegSet below.
@@ -131,7 +138,11 @@ class FloatRegisterImpl: public AbstractRegisterImpl {
  public:
   enum {
     number_of_registers     = 32,
-    max_slots_per_register  = 2
+    max_slots_per_register  = 2,
+
+    // C-Ext: float registers in the range of [f8~f15] are correspond for RVC. Please see Table 16.2 in spec.
+    compressed_register_base = 8,
+    compressed_register_top  = 15,
   };
 
   // construction
@@ -144,8 +155,11 @@ class FloatRegisterImpl: public AbstractRegisterImpl {
 
   // accessors
   int   encoding() const                          { assert(is_valid(), "invalid register"); return (intptr_t)this; }
+  int   compressed_encoding() const               { assert(is_compressed_valid(), "invalid compressed register"); return ((intptr_t)this - compressed_register_base); }
   int   encoding_nocheck() const                         { return (intptr_t)this; }
+  int   compressed_encoding_nocheck() const       { return ((intptr_t)this - compressed_register_base); }
   bool  is_valid() const                          { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
+  bool  is_compressed_valid() const               { return compressed_register_base <= (intptr_t)this && (intptr_t)this <= compressed_register_top; }
   const char* name() const;
 
 };

src/hotspot/cpu/riscv/register_riscv.hpp

@@ -1156,28 +1156,27 @@ bool needs_acquiring_load_reserved(const Node *n)
 
 int MachCallStaticJavaNode::ret_addr_offset()
 {
-  // call should be a simple jal
-  int off = 4;
-  return off;
+  // jal
+  return 1 * NativeInstruction::instruction_size;
 }
 
 int MachCallDynamicJavaNode::ret_addr_offset()
 {
-  return 28; // movptr, jal
+  return 7 * NativeInstruction::instruction_size; // movptr, jal
 }
 
 int MachCallRuntimeNode::ret_addr_offset() {
   // for generated stubs the call will be
   //   jal(addr)
   // or with far branches
   //   jal(trampoline_stub)
-  // for real runtime callouts it will be five instructions
+  // for real runtime callouts it will be 11 instructions
   // see riscv64_enc_java_to_runtime
-  //   la(t1, retaddr)
-  //   la(t0, RuntimeAddress(addr))
-  //   addi(sp, sp, -2 * wordSize)
-  //   sd(t1, Address(sp, wordSize))
-  //   jalr(t0)
+  //   la(t1, retaddr)                ->  auipc + addi
+  //   la(t0, RuntimeAddress(addr))   ->  lui + addi + slli + addi + slli + addi
+  //   addi(sp, sp, -2 * wordSize)    ->  addi
+  //   sd(t1, Address(sp, wordSize))  ->  sd
+  //   jalr(t0)                       ->  jalr
   CodeBlob *cb = CodeCache::find_blob(_entry_point);
   if (cb != NULL) {
     return 1 * NativeInstruction::instruction_size;

src/hotspot/cpu/riscv/riscv.ad

@@ -106,6 +106,12 @@ void VM_Version::initialize() {
     FLAG_SET_DEFAULT(UseMD5Intrinsics, false);
   }
 
+  // compressed instruction extension
+  if (UseRVC && !(_features & CPU_C)) {
+    warning("RVC is not supported on this CPU");
+    FLAG_SET_DEFAULT(UseRVC, false);
+  }
+
   if (UseRVV) {
     if (!(_features & CPU_V)) {
       warning("RVV is not supported on this CPU");