Remove useless and polish comments

Author: zhengxiaolinX

src/hotspot/cpu/riscv/assembler_riscv.hpp

@@ -2023,19 +2023,19 @@ enum Nf {
 // RISC-V Compressed Instructions Extension
 // ========================================
 // Note:
-//   1. When UseRVC is enabled, 32-bit instructions under 'CompressibleRegion's will be
-//      transformed to 16-bit instructions if compressible.
-//   2. RVC instructions in Assembler always begin with 'c_' prefix, as 'c_li',
-//      but most of time we have no need to explicitly use these instructions.
-//   3. We introduce 'CompressibleRegion' to hint instructions in this Region's RTTI range
-//      are qualified to change to their 2-byte versions.
-//      An example:
+// 1. When UseRVC is enabled, 32-bit instructions under 'CompressibleRegion's will be
+//    transformed to 16-bit instructions if compressible.
+// 2. RVC instructions in Assembler always begin with 'c_' prefix, as 'c_li',
+//    but most of time we have no need to explicitly use these instructions.
+// 3. We introduce 'CompressibleRegion' to hint instructions in this Region's RTTI range
+//    are qualified to change to their 2-byte versions.
+//    An example:
 //
-//        CompressibleRegion cr(_masm);
-//        __ andr(...);      // this instruction could change to c.and if able to
+//      CompressibleRegion cr(_masm);
+//      __ andr(...);      // this instruction could change to c.and if able to
 //
-//   4. Using -XX:PrintAssemblyOptions=no-aliases could print RVC instructions instead of
-//      normal ones.
+// 4. Using -XX:PrintAssemblyOptions=no-aliases could print RVC instructions instead of
+//    normal ones.
 //
 
 private:
@@ -2061,23 +2061,6 @@ enum Nf {
     }
   };
 
-  // RVC: extract a 16-bit instruction.
-  static inline uint16_t c_extract(uint16_t val, unsigned msb, unsigned lsb) {
-    assert_cond(msb >= lsb && msb <= 15);
-    unsigned nbits = msb - lsb + 1;
-    uint16_t mask = (1U << nbits) - 1;
-    uint16_t result = val >> lsb;
-    result &= mask;
-    return result;
-  }
-
-  static inline int16_t c_sextract(uint16_t val, unsigned msb, unsigned lsb) {
-    assert_cond(msb >= lsb && msb <= 15);
-    int16_t result = val << (15 - msb);
-    result >>= (15 - msb + lsb);
-    return result;
-  }
-
   // RVC: patch a 16-bit instruction.
   static void c_patch(address a, unsigned msb, unsigned lsb, uint16_t val) {
     assert_cond(a != NULL);

src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp

@@ -1325,7 +1325,7 @@ void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Op
 void LIR_Assembler::align_call(LIR_Code code) {
   // RVC: With RVC a call may get 2-byte aligned.
   //   the address of jal itself (which will be patched later) should not span the cache line.
-  //   See CallDynamicJavaDirectNode::compute_padding() for more info.
+  //   See CallStaticJavaDirectNode::compute_padding() for more info.
   __ align(4);
 }
 

src/hotspot/cpu/riscv/riscv.ad

@@ -1191,7 +1191,7 @@ int MachCallNativeNode::ret_addr_offset() {
 }
 
 // RVC: With RVC a call may get 2-byte aligned.
-//   The offset encoding in jal ranges bits [12, 31], which could span the cache line.
+//   The offset encoding in jal ranges bits [12, 31] could span the cache line.
 //   Patching this unaligned address will make the write operation not atomic.
 //   Other threads may be running the same piece of code at full speed, causing concurrency issues.
 //   So we must ensure that it does not span a cache line so that it can be patched.
@@ -1201,11 +1201,7 @@ int CallStaticJavaDirectNode::compute_padding(int current_offset) const
   return align_up(current_offset, alignment_required()) - current_offset;
 }
 
-// RVC: With RVC a call may get 2-byte aligned.
-//   The offset encoding in jal ranges bits [12, 31], which could span the cache line.
-//   Patching this unaligned address will make the write operation not atomic.
-//   Other threads may be running the same piece of code at full speed, causing concurrency issues.
-//   So we must ensure that it does not span a cache line so that it can be patched.
+// RVC: See CallStaticJavaDirectNode::compute_padding() for more info.
 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
 {
   // skip the movptr in MacroAssembler::ic_call():

src/hotspot/cpu/riscv/vm_version_riscv.cpp

@@ -101,12 +101,6 @@ void VM_Version::initialize() {
     FLAG_SET_DEFAULT(UseMD5Intrinsics, false);
   }
 
-  // compressed instruction extension
-  if (UseRVC && !(_features & CPU_C)) {
-    warning("RVC is not supported on this CPU");
-    FLAG_SET_DEFAULT(UseRVC, false);
-  }
-
   if (UseRVV) {
     if (!(_features & CPU_V)) {
       warning("RVV is not supported on this CPU");
@@ -122,6 +116,11 @@ void VM_Version::initialize() {
     FLAG_SET_DEFAULT(UseRVB, false);
   }
 
+  if (UseRVC && !(_features & CPU_C)) {
+    warning("RVC is not supported on this CPU");
+    FLAG_SET_DEFAULT(UseRVC, false);
+  }
+
   if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
     FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
   }