Skip to content

Commit f3c980c

Browse files
author
Fei Yang
committed
Merge branch 'master' into riscv-port
2 parents aa0aaf8 + 5dcdee4 commit f3c980c

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

44 files changed

+599
-501
lines changed

‎src/hotspot/cpu/aarch64/aarch64.ad‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2481,7 +2481,7 @@ const RegMask* Matcher::predicate_reg_mask(void) {
24812481
return &_PR_REG_mask;
24822482
}
24832483

2484-
const TypeVect* Matcher::predicate_reg_type(const Type* elemTy, int length) {
2484+
const TypeVectMask* Matcher::predicate_reg_type(const Type* elemTy, int length) {
24852485
return new TypeVectMask(elemTy, length);
24862486
}
24872487

‎src/hotspot/cpu/aarch64/aarch64_sve.ad‎

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5744,4 +5744,19 @@ instruct vmask_lasttrue_partial(iRegINoSp dst, pReg src, pReg ptmp, rFlagsReg cr
57445744
__ sve_vmask_lasttrue($dst$$Register, bt, as_PRegister($ptmp$$reg), as_PRegister($ptmp$$reg));
57455745
%}
57465746
ins_pipe(pipe_slow);
5747-
%}
5747+
%}
5748+
5749+
// ---------------------------- Vector mask generation ---------------------------
5750+
instruct vmask_gen(pRegGov pg, iRegL len, rFlagsReg cr) %{
5751+
predicate(UseSVE > 0);
5752+
match(Set pg (VectorMaskGen len));
5753+
effect(KILL cr);
5754+
ins_cost(SVE_COST);
5755+
format %{ "sve_whilelo $pg, zr, $len\t # sve" %}
5756+
ins_encode %{
5757+
BasicType bt = Matcher::vector_element_basic_type(this);
5758+
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
5759+
__ sve_whilelo(as_PRegister($pg$$reg), size, zr, as_Register($len$$reg));
5760+
%}
5761+
ins_pipe(pipe_slow);
5762+
%}

‎src/hotspot/cpu/aarch64/aarch64_sve_ad.m4‎

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3174,4 +3174,19 @@ instruct vmask_lasttrue_partial(iRegINoSp dst, pReg src, pReg ptmp, rFlagsReg cr
31743174
__ sve_vmask_lasttrue($dst$$Register, bt, as_PRegister($ptmp$$reg), as_PRegister($ptmp$$reg));
31753175
%}
31763176
ins_pipe(pipe_slow);
3177-
%}dnl
3177+
%}
3178+
3179+
// ---------------------------- Vector mask generation ---------------------------
3180+
instruct vmask_gen(pRegGov pg, iRegL len, rFlagsReg cr) %{
3181+
predicate(UseSVE > 0);
3182+
match(Set pg (VectorMaskGen len));
3183+
effect(KILL cr);
3184+
ins_cost(SVE_COST);
3185+
format %{ "sve_whilelo $pg, zr, $len\t # sve" %}
3186+
ins_encode %{
3187+
BasicType bt = Matcher::vector_element_basic_type(this);
3188+
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
3189+
__ sve_whilelo(as_PRegister($pg$$reg), size, zr, as_Register($len$$reg));
3190+
%}
3191+
ins_pipe(pipe_slow);
3192+
%}

‎src/hotspot/cpu/aarch64/vm_version_aarch64.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -469,6 +469,14 @@ void VM_Version::initialize() {
469469
}
470470
}
471471

472+
int inline_size = (UseSVE > 0 && MaxVectorSize >= 16) ? MaxVectorSize : 0;
473+
if (FLAG_IS_DEFAULT(ArrayOperationPartialInlineSize)) {
474+
FLAG_SET_DEFAULT(ArrayOperationPartialInlineSize, inline_size);
475+
} else if (ArrayOperationPartialInlineSize != 0 && ArrayOperationPartialInlineSize != inline_size) {
476+
warning("Setting ArrayOperationPartialInlineSize to %d", inline_size);
477+
ArrayOperationPartialInlineSize = inline_size;
478+
}
479+
472480
if (FLAG_IS_DEFAULT(OptoScheduling)) {
473481
OptoScheduling = true;
474482
}

‎src/hotspot/cpu/arm/arm.ad‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -991,7 +991,7 @@ const RegMask* Matcher::predicate_reg_mask(void) {
991991
return NULL;
992992
}
993993

994-
const TypeVect* Matcher::predicate_reg_type(const Type* elemTy, int length) {
994+
const TypeVectMask* Matcher::predicate_reg_type(const Type* elemTy, int length) {
995995
return NULL;
996996
}
997997

‎src/hotspot/cpu/ppc/ppc.ad‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2185,7 +2185,7 @@ const RegMask* Matcher::predicate_reg_mask(void) {
21852185
return NULL;
21862186
}
21872187

2188-
const TypeVect* Matcher::predicate_reg_type(const Type* elemTy, int length) {
2188+
const TypeVectMask* Matcher::predicate_reg_type(const Type* elemTy, int length) {
21892189
return NULL;
21902190
}
21912191

‎src/hotspot/cpu/riscv/riscv.ad‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1795,7 +1795,7 @@ const RegMask* Matcher::predicate_reg_mask(void) {
17951795
return NULL;
17961796
}
17971797

1798-
const TypeVect* Matcher::predicate_reg_type(const Type* elemTy, int length) {
1798+
const TypeVectMask* Matcher::predicate_reg_type(const Type* elemTy, int length) {
17991799
return NULL;
18001800
}
18011801

‎src/hotspot/cpu/s390/s390.ad‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1544,7 +1544,7 @@ const RegMask* Matcher::predicate_reg_mask(void) {
15441544
return NULL;
15451545
}
15461546

1547-
const TypeVect* Matcher::predicate_reg_type(const Type* elemTy, int length) {
1547+
const TypeVectMask* Matcher::predicate_reg_type(const Type* elemTy, int length) {
15481548
return NULL;
15491549
}
15501550

‎src/hotspot/cpu/x86/x86.ad‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2051,7 +2051,7 @@ const RegMask* Matcher::predicate_reg_mask(void) {
20512051
return &_VECTMASK_REG_mask;
20522052
}
20532053

2054-
const TypeVect* Matcher::predicate_reg_type(const Type* elemTy, int length) {
2054+
const TypeVectMask* Matcher::predicate_reg_type(const Type* elemTy, int length) {
20552055
return new TypeVectMask(elemTy, length);
20562056
}
20572057

0 commit comments

Comments
 (0)