de0_nano: Add description of the de0 nano startup

Author: stffrdhrn

or1k-dev.tcl de0_nano/de0_nano.cfgor1k-dev.tcl renamed to de0_nano/de0_nano.cfg

@@ -1,15 +1,14 @@
-# If you want to use the VJTAG TAP or the XILINX BSCAN,
-# you must set your FPGA TAP ID here
-
+# The de0 nano TAPID
 set FPGATAPID 0x020f30dd
 
-# Choose your TAP core (VJTAG , MOHOR or XILINX_BSCAN)
+# Choose your TAP core (VJTAG, VJTAG_VPI or XILINX_BSCAN)
+# De0 nano uses VJTAG
 if { [info exists TAP_TYPE] == 0} {
    set TAP_TYPE VJTAG
 }
 
 # Set your chip name
-set CHIPNAME or1200
+set CHIPNAME mor1kx
 
 source [find target/or1k.cfg]
 
@@ -19,11 +18,6 @@ poll_period 1
 # Enable the target description feature
 gdb_target_description enable
 
-# Add a new register in the cpu register list. This register will be
-# included in the generated target descriptor file.
-# format is addreg [name] [address] [feature] [reg_group]
-addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
-
 # Override default init_reset
 proc init_reset {mode} {
 	soft_reset_halt
@@ -48,4 +42,3 @@ set c_blue  "\033\[01;34m"
 set c_reset "\033\[0m"
 
 puts [format "%sTarget ready...%s" $c_blue $c_reset]
-

de0_nano/index.md

@@ -10,7 +10,7 @@ parent: FuseSoC
 
  * An x86 Linux workstation
  * The `curl` command line utilities
- * OpenOCD
+ * OpenOCD 0.10.0 (As of 2025, versions 0.11.0 and 0.12.0 have jtag timing issues)
  * The quartus FPGA design software
  * `fusesoc` - The [FuseSoC build system](../fusesoc.html).
  * `or1k-elf-` Toolchain as installed in our [newlib tutorial](../newlib.html).
@@ -59,6 +59,7 @@ cd /tmp/or1k-de0nano
 
 curl -L -O https://openrisc.io/tutorials/sw/hello/hello.c
 curl -L -O https://openrisc.io/tutorials/sw/timer/timer.c
+curl -L -O https://openrisc.io/tutorials/de0_nano/de0_nano.cfg
 
 CFLAGS="-mboard=de0_nano -DDE0_NANO"
 or1k-elf-gcc -g -Og $CFLAGS -o hello.elf hello.c
@@ -106,7 +107,7 @@ board.
 
 In one terminal execute the following command:
 
-	openocd -s ${OPENOCD}/share/openocd/scripts/ -f interface/altera-usb-blaster.cfg -f ../or1k-dev.tcl
+	openocd -f interface/altera-usb-blaster.cfg -f de0_nano.cfg
 
 ### Run software with gdb
 
@@ -122,4 +123,14 @@ In gdb execute the following steps:
 	set $npc=0x100
 	continue
 
+This will:
+
+ - Connect GDB to the GDB server hosted in the openocd process.
+ - The `load` command will load the `timer.elf` binary onto the de0 nano
+   board.
+ - The `set $npc=0x100` command will set the mor1kx CPU program counter to
+   `0x100` the default reset verctor.
+ - Finally `continue` will resume the program. In this case it will resume
+   from reset starting the program.
+
 You should see the LEDs counting and UART output once a second.

pack.sh

@@ -8,7 +8,6 @@ Makefile
 README.md
 bootstrap-quick-start.sh
 environment.sh
-or1k-dev.tcl
 sw/hello/hello.c
 sw/timer/timer.c
 or1ksim/Makefile
@@ -21,6 +20,7 @@ de0_nano/README.md
 de0_nano/de0_nano.sof
 de0_nano/hello.elf
 de0_nano/timer.elf
+de0_nano/de0_nano.cfg
 docs/Debugging.md
 "