security detection and trace information for CPU

[Liyang131313]

Hello, I would like to ask a few questions:

1. Can the Software Trace Module (STM) track the access information? Examples of memory transfer signals include memory address, transfer direction (read/write), ID of the IP core making the memory transfer (master id ), transfer privileges, etc

2. Can I take the signal from the Debug network (or maybe “Core Trace Module (CTM)”) in debug mode and transfer it to my own verilog module on the AXI bus for security detection?