UCS/SYS/TOPO: Added bw estimation for Sapphire Rapids family.

Author: rakhmets

src/tools/info/sys_info.c

@@ -22,21 +22,22 @@
 
 
 static const char *cpu_model_names[] = {
-    [UCS_CPU_MODEL_UNKNOWN]            = "unknown",
-    [UCS_CPU_MODEL_INTEL_IVYBRIDGE]    = "IvyBridge",
-    [UCS_CPU_MODEL_INTEL_SANDYBRIDGE]  = "SandyBridge",
-    [UCS_CPU_MODEL_INTEL_NEHALEM]      = "Nehalem",
-    [UCS_CPU_MODEL_INTEL_WESTMERE]     = "Westmere",
-    [UCS_CPU_MODEL_INTEL_HASWELL]      = "Haswell",
-    [UCS_CPU_MODEL_INTEL_BROADWELL]    = "Broadwell",
-    [UCS_CPU_MODEL_INTEL_SKYLAKE]      = "Skylake",
-    [UCS_CPU_MODEL_ARM_AARCH64]        = "ARM 64-bit",
-    [UCS_CPU_MODEL_AMD_NAPLES]         = "Naples",
-    [UCS_CPU_MODEL_AMD_ROME]           = "Rome",
-    [UCS_CPU_MODEL_AMD_MILAN]          = "Milan",
-    [UCS_CPU_MODEL_ZHAOXIN_ZHANGJIANG] = "Zhangjiang",
-    [UCS_CPU_MODEL_ZHAOXIN_WUDAOKOU]   = "Wudaokou",
-    [UCS_CPU_MODEL_ZHAOXIN_LUJIAZUI]   = "Lujiazui"
+    [UCS_CPU_MODEL_UNKNOWN]              = "unknown",
+    [UCS_CPU_MODEL_INTEL_IVYBRIDGE]      = "IvyBridge",
+    [UCS_CPU_MODEL_INTEL_SANDYBRIDGE]    = "SandyBridge",
+    [UCS_CPU_MODEL_INTEL_NEHALEM]        = "Nehalem",
+    [UCS_CPU_MODEL_INTEL_WESTMERE]       = "Westmere",
+    [UCS_CPU_MODEL_INTEL_HASWELL]        = "Haswell",
+    [UCS_CPU_MODEL_INTEL_BROADWELL]      = "Broadwell",
+    [UCS_CPU_MODEL_INTEL_SKYLAKE]        = "Skylake",
+    [UCS_CPU_MODEL_INTEL_SAPPHIRERAPIDS] = "SapphireRapids",
+    [UCS_CPU_MODEL_ARM_AARCH64]          = "ARM 64-bit",
+    [UCS_CPU_MODEL_AMD_NAPLES]           = "Naples",
+    [UCS_CPU_MODEL_AMD_ROME]             = "Rome",
+    [UCS_CPU_MODEL_AMD_MILAN]            = "Milan",
+    [UCS_CPU_MODEL_ZHAOXIN_ZHANGJIANG]   = "Zhangjiang",
+    [UCS_CPU_MODEL_ZHAOXIN_WUDAOKOU]     = "Wudaokou",
+    [UCS_CPU_MODEL_ZHAOXIN_LUJIAZUI]     = "Lujiazui"
 };
 
 static const char* cpu_vendor_names[] = {

src/ucs/arch/cpu.h

@@ -28,6 +28,7 @@ typedef enum ucs_cpu_model {
     UCS_CPU_MODEL_INTEL_HASWELL,
     UCS_CPU_MODEL_INTEL_BROADWELL,
     UCS_CPU_MODEL_INTEL_SKYLAKE,
+    UCS_CPU_MODEL_INTEL_SAPPHIRERAPIDS,
     UCS_CPU_MODEL_ARM_AARCH64,
     UCS_CPU_MODEL_AMD_NAPLES,
     UCS_CPU_MODEL_AMD_ROME,

src/ucs/arch/x86_64/cpu.c

@@ -453,6 +453,9 @@ ucs_cpu_model_t ucs_arch_get_cpu_model()
             case 0x55:
                 cpu_model = UCS_CPU_MODEL_INTEL_SKYLAKE;
                 break;
+            case 0x8f:
+                cpu_model = UCS_CPU_MODEL_INTEL_SAPPHIRERAPIDS;
+                break;
             }
             break;
         /* AMD Zen2 */

src/ucs/sys/topo/base/topo.c

@@ -308,6 +308,9 @@ static void ucs_topo_sys_root_distance(ucs_sys_dev_distance_t *distance)
 {
     distance->latency = 500e-9;
     switch (ucs_arch_get_cpu_model()) {
+    case UCS_CPU_MODEL_INTEL_SAPPHIRERAPIDS:
+        distance->bandwidth = 23288 * UCS_MBYTE;
+        break;
     case UCS_CPU_MODEL_AMD_ROME:
     case UCS_CPU_MODEL_AMD_MILAN:
         distance->bandwidth = 5100 * UCS_MBYTE;