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UCT/IB: Use relaxed ordering for Intel Emerald Rapids CPUs #10955

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UCT/IB: Use relaxed ordering for Intel Emerald Rapids CPUs #10955

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41 changes: 21 additions & 20 deletions src/ucs/arch/cpu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -178,26 +178,27 @@ const char *ucs_cpu_vendor_name()
const char *ucs_cpu_model_name()
{
static const char *cpu_model_names[] = {
[UCS_CPU_MODEL_UNKNOWN] = UCS_VALUE_UNKNOWN_STR,
[UCS_CPU_MODEL_INTEL_IVYBRIDGE] = "IvyBridge",
[UCS_CPU_MODEL_INTEL_SANDYBRIDGE] = "SandyBridge",
[UCS_CPU_MODEL_INTEL_NEHALEM] = "Nehalem",
[UCS_CPU_MODEL_INTEL_WESTMERE] = "Westmere",
[UCS_CPU_MODEL_INTEL_HASWELL] = "Haswell",
[UCS_CPU_MODEL_INTEL_BROADWELL] = "Broadwell",
[UCS_CPU_MODEL_INTEL_SKYLAKE] = "Skylake",
[UCS_CPU_MODEL_INTEL_ICELAKE] = "Icelake",
[UCS_CPU_MODEL_ARM_AARCH64] = "ARM 64-bit",
[UCS_CPU_MODEL_AMD_NAPLES] = "Naples",
[UCS_CPU_MODEL_AMD_ROME] = "Rome",
[UCS_CPU_MODEL_AMD_MILAN] = "Milan",
[UCS_CPU_MODEL_AMD_GENOA] = "Genoa",
[UCS_CPU_MODEL_AMD_TURIN] = "Turin",
[UCS_CPU_MODEL_ZHAOXIN_ZHANGJIANG] = "Zhangjiang",
[UCS_CPU_MODEL_ZHAOXIN_WUDAOKOU] = "Wudaokou",
[UCS_CPU_MODEL_ZHAOXIN_LUJIAZUI] = "Lujiazui",
[UCS_CPU_MODEL_RV64G] = "RV64G",
[UCS_CPU_MODEL_NVIDIA_GRACE] = "Grace"
[UCS_CPU_MODEL_UNKNOWN] = UCS_VALUE_UNKNOWN_STR,
[UCS_CPU_MODEL_INTEL_IVYBRIDGE] = "IvyBridge",
[UCS_CPU_MODEL_INTEL_SANDYBRIDGE] = "SandyBridge",
[UCS_CPU_MODEL_INTEL_NEHALEM] = "Nehalem",
[UCS_CPU_MODEL_INTEL_WESTMERE] = "Westmere",
[UCS_CPU_MODEL_INTEL_HASWELL] = "Haswell",
[UCS_CPU_MODEL_INTEL_BROADWELL] = "Broadwell",
[UCS_CPU_MODEL_INTEL_SKYLAKE] = "Skylake",
[UCS_CPU_MODEL_INTEL_ICELAKE] = "Icelake",
[UCS_CPU_MODEL_INTEL_EMERALD_RAPIDS] = "Emerald Rapids",
[UCS_CPU_MODEL_ARM_AARCH64] = "ARM 64-bit",
[UCS_CPU_MODEL_AMD_NAPLES] = "Naples",
[UCS_CPU_MODEL_AMD_ROME] = "Rome",
[UCS_CPU_MODEL_AMD_MILAN] = "Milan",
[UCS_CPU_MODEL_AMD_GENOA] = "Genoa",
[UCS_CPU_MODEL_AMD_TURIN] = "Turin",
[UCS_CPU_MODEL_ZHAOXIN_ZHANGJIANG] = "Zhangjiang",
[UCS_CPU_MODEL_ZHAOXIN_WUDAOKOU] = "Wudaokou",
[UCS_CPU_MODEL_ZHAOXIN_LUJIAZUI] = "Lujiazui",
[UCS_CPU_MODEL_RV64G] = "RV64G",
[UCS_CPU_MODEL_NVIDIA_GRACE] = "Grace"
};

return cpu_model_names[ucs_arch_get_cpu_model()];
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5 changes: 4 additions & 1 deletion src/ucs/arch/cpu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,7 @@ typedef enum ucs_cpu_model {
UCS_CPU_MODEL_INTEL_BROADWELL,
UCS_CPU_MODEL_INTEL_SKYLAKE,
UCS_CPU_MODEL_INTEL_ICELAKE,
UCS_CPU_MODEL_INTEL_EMERALD_RAPIDS,
UCS_CPU_MODEL_ARM_AARCH64,
UCS_CPU_MODEL_AMD_NAPLES,
UCS_CPU_MODEL_AMD_ROME,
Expand Down Expand Up @@ -166,7 +167,9 @@ static inline int ucs_cpu_prefer_relaxed_order()
(cpu_model == UCS_CPU_MODEL_AMD_ROME) ||
(cpu_model == UCS_CPU_MODEL_AMD_MILAN) ||
(cpu_model == UCS_CPU_MODEL_AMD_GENOA) ||
(cpu_model == UCS_CPU_MODEL_AMD_TURIN)));
(cpu_model == UCS_CPU_MODEL_AMD_TURIN))) ||
((cpu_vendor == UCS_CPU_VENDOR_INTEL) &&
(cpu_model == UCS_CPU_MODEL_INTEL_EMERALD_RAPIDS));
}


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3 changes: 3 additions & 0 deletions src/ucs/arch/x86_64/cpu.c
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Expand Up @@ -459,6 +459,9 @@ ucs_cpu_model_t ucs_arch_get_cpu_model()
case 0x7e:
cpu_model = UCS_CPU_MODEL_INTEL_ICELAKE;
break;
case 0xcf:
cpu_model = UCS_CPU_MODEL_INTEL_EMERALD_RAPIDS;
break;
}
break;
/* AMD Zen2 */
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