diff --git a/src/ucs/arch/cpu.h b/src/ucs/arch/cpu.h
index f75fc32f5be..79e2f61b617 100644
--- a/src/ucs/arch/cpu.h
+++ b/src/ucs/arch/cpu.h
@@ -169,6 +169,15 @@ static inline int ucs_cpu_prefer_relaxed_order()
              (cpu_model == UCS_CPU_MODEL_AMD_TURIN)));
 }
 
+static inline int ucs_cpu_prefer_odp()
+{
+    ucs_cpu_vendor_t cpu_vendor = ucs_arch_get_cpu_vendor();
+    ucs_cpu_model_t cpu_model   = ucs_arch_get_cpu_model();
+
+    return ((cpu_vendor == UCS_CPU_VENDOR_NVIDIA) &&
+            (cpu_model == UCS_CPU_MODEL_NVIDIA_GRACE));
+}
+
 
 #define UCS_CPU_VENDOR_LABEL "CPU vendor"
 #define UCS_CPU_MODEL_LABEL  "CPU model"
diff --git a/src/uct/ib/mlx5/dv/ib_mlx5dv_md.c b/src/uct/ib/mlx5/dv/ib_mlx5dv_md.c
index 08a7a9e28f5..90796b70e82 100644
--- a/src/uct/ib/mlx5/dv/ib_mlx5dv_md.c
+++ b/src/uct/ib/mlx5/dv/ib_mlx5dv_md.c
@@ -1782,6 +1782,9 @@ static void uct_ib_mlx5_devx_check_odp(uct_ib_mlx5_md_t *md,
             (UCS_BIT(UCT_IB_DEVX_OBJ_RCQP) | UCS_BIT(UCT_IB_DEVX_OBJ_DCI))) {
             reason = "version 1 is not supported for DevX QP";
             goto no_odp;
+        } else if (ucs_cpu_prefer_odp()) {
+            ucs_warn("%s: devx objects are disabled in ucx.conf, the performance may be degraded, as ODPv2 is not supported",
+               uct_ib_device_name(&md->super.dev));
         }
 
         odp_cap = UCT_IB_MLX5DV_ADDR_OF(