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14 files changed

+186
-91
lines changed

14 files changed

+186
-91
lines changed

‎crates/vm/src/arch/integration_api.rs‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -334,7 +334,8 @@ pub struct VecHeapBranchAdapterInterface<
334334
>(PhantomData<T>);
335335

336336
impl<T, const NUM_READS: usize, const BLOCKS_PER_READ: usize, const READ_SIZE: usize>
337-
VmAdapterInterface<T> for VecHeapBranchAdapterInterface<T, NUM_READS, BLOCKS_PER_READ, READ_SIZE>
337+
VmAdapterInterface<T>
338+
for VecHeapBranchAdapterInterface<T, NUM_READS, BLOCKS_PER_READ, READ_SIZE>
338339
{
339340
type Reads = [[[T; READ_SIZE]; BLOCKS_PER_READ]; NUM_READS];
340341
type Writes = ();
@@ -848,7 +849,10 @@ mod conversions {
848849
BasicAdapterInterface<T, ImmInstruction<T>, BASIC_NUM_READS, 0, READ_SIZE, 0>,
849850
>,
850851
>
851-
for AdapterAirContext<T, VecHeapBranchAdapterInterface<T, NUM_READS, BLOCKS_PER_READ, READ_SIZE>>
852+
for AdapterAirContext<
853+
T,
854+
VecHeapBranchAdapterInterface<T, NUM_READS, BLOCKS_PER_READ, READ_SIZE>,
855+
>
852856
{
853857
fn from(
854858
ctx: AdapterAirContext<

‎crates/vm/src/arch/testing/cpu.rs‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -185,7 +185,11 @@ where
185185
let register = self.get_default_register(reg_increment);
186186
let pointer = self.get_default_pointer(pointer_increment);
187187
// Cast to u32 to ensure we write exactly 4 bytes (RV32 register size).
188-
self.write(1, register, (pointer as u32).to_le_bytes().map(F::from_canonical_u8));
188+
self.write(
189+
1,
190+
register,
191+
(pointer as u32).to_le_bytes().map(F::from_canonical_u8),
192+
);
189193
(register, pointer)
190194
}
191195

‎crates/vm/src/arch/testing/cuda.rs‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -218,7 +218,11 @@ impl TestBuilder<F> for GpuChipTestBuilder {
218218
let register = self.get_default_register(reg_increment);
219219
let pointer = self.get_default_pointer(pointer_increment);
220220
// Cast to u32 to ensure we write exactly 4 bytes (RV32 register size).
221-
self.write(1, register, (pointer as u32).to_le_bytes().map(F::from_canonical_u8));
221+
self.write(
222+
1,
223+
register,
224+
(pointer as u32).to_le_bytes().map(F::from_canonical_u8),
225+
);
222226
(register, pointer)
223227
}
224228

‎crates/vm/src/system/cuda/memory.rs‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,9 @@
11
use std::sync::Arc;
22

33
use openvm_circuit::{
4-
arch::{AddressSpaceHostLayout, CONST_BLOCK_SIZE, DenseRecordArena, MemoryConfig, ADDR_SPACE_OFFSET},
4+
arch::{
5+
AddressSpaceHostLayout, DenseRecordArena, MemoryConfig, ADDR_SPACE_OFFSET, CONST_BLOCK_SIZE,
6+
},
57
system::{
68
memory::{online::LinearMemory, AddressMap, TimestampedValues},
79
TouchedMemory,

‎extensions/bigint/circuit/src/base_alu.rs‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -139,10 +139,10 @@ unsafe fn execute_e12_impl<F: PrimeField32, CTX: ExecutionCtxTrait, OP: AluOp>(
139139
let rs1_ptr = exec_state.vm_read_no_adapter::<u8, 4>(RV32_REGISTER_AS, pre_compute.b as u32);
140140
let rs2_ptr = exec_state.vm_read_no_adapter::<u8, 4>(RV32_REGISTER_AS, pre_compute.c as u32);
141141
let rd_ptr = exec_state.vm_read_no_adapter::<u8, 4>(RV32_REGISTER_AS, pre_compute.a as u32);
142-
let rs1 =
143-
exec_state.vm_read_no_adapter::<u8, INT256_NUM_LIMBS>(RV32_MEMORY_AS, u32::from_le_bytes(rs1_ptr));
144-
let rs2 =
145-
exec_state.vm_read_no_adapter::<u8, INT256_NUM_LIMBS>(RV32_MEMORY_AS, u32::from_le_bytes(rs2_ptr));
142+
let rs1 = exec_state
143+
.vm_read_no_adapter::<u8, INT256_NUM_LIMBS>(RV32_MEMORY_AS, u32::from_le_bytes(rs1_ptr));
144+
let rs2 = exec_state
145+
.vm_read_no_adapter::<u8, INT256_NUM_LIMBS>(RV32_MEMORY_AS, u32::from_le_bytes(rs2_ptr));
146146
let rd = <OP as AluOp>::compute(rs1, rs2);
147147
exec_state.vm_write_no_adapter(RV32_MEMORY_AS, u32::from_le_bytes(rd_ptr), &rd);
148148
let pc = exec_state.pc();

‎extensions/bigint/circuit/src/branch_eq.rs‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,9 @@ use openvm_rv32im_circuit::BranchEqualExecutor;
1313
use openvm_rv32im_transpiler::BranchEqualOpcode;
1414
use openvm_stark_backend::p3_field::PrimeField32;
1515

16-
use crate::{common::bytes_to_u64_array, BranchAdapterExecutor, Rv32BranchEqual256Executor, INT256_NUM_LIMBS};
16+
use crate::{
17+
common::bytes_to_u64_array, BranchAdapterExecutor, Rv32BranchEqual256Executor, INT256_NUM_LIMBS,
18+
};
1719

1820
impl Rv32BranchEqual256Executor {
1921
pub fn new(adapter_step: BranchAdapterExecutor, offset: usize, pc_step: u32) -> Self {
@@ -128,10 +130,10 @@ unsafe fn execute_e12_impl<F: PrimeField32, CTX: ExecutionCtxTrait, const IS_NE:
128130
let mut pc = exec_state.pc();
129131
let rs1_ptr = exec_state.vm_read_no_adapter::<u8, 4>(RV32_REGISTER_AS, pre_compute.a as u32);
130132
let rs2_ptr = exec_state.vm_read_no_adapter::<u8, 4>(RV32_REGISTER_AS, pre_compute.b as u32);
131-
let rs1 =
132-
exec_state.vm_read_no_adapter::<u8, INT256_NUM_LIMBS>(RV32_MEMORY_AS, u32::from_le_bytes(rs1_ptr));
133-
let rs2 =
134-
exec_state.vm_read_no_adapter::<u8, INT256_NUM_LIMBS>(RV32_MEMORY_AS, u32::from_le_bytes(rs2_ptr));
133+
let rs1 = exec_state
134+
.vm_read_no_adapter::<u8, INT256_NUM_LIMBS>(RV32_MEMORY_AS, u32::from_le_bytes(rs1_ptr));
135+
let rs2 = exec_state
136+
.vm_read_no_adapter::<u8, INT256_NUM_LIMBS>(RV32_MEMORY_AS, u32::from_le_bytes(rs2_ptr));
135137
let cmp_result = u256_eq(rs1, rs2);
136138
if cmp_result ^ IS_NE {
137139
pc = (pc as isize + pre_compute.imm) as u32;

‎extensions/bigint/circuit/src/branch_lt.rs‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -136,10 +136,10 @@ unsafe fn execute_e12_impl<F: PrimeField32, CTX: ExecutionCtxTrait, OP: BranchLe
136136
let mut pc = exec_state.pc();
137137
let rs1_ptr = exec_state.vm_read_no_adapter::<u8, 4>(RV32_REGISTER_AS, pre_compute.a as u32);
138138
let rs2_ptr = exec_state.vm_read_no_adapter::<u8, 4>(RV32_REGISTER_AS, pre_compute.b as u32);
139-
let rs1 =
140-
exec_state.vm_read_no_adapter::<u8, INT256_NUM_LIMBS>(RV32_MEMORY_AS, u32::from_le_bytes(rs1_ptr));
141-
let rs2 =
142-
exec_state.vm_read_no_adapter::<u8, INT256_NUM_LIMBS>(RV32_MEMORY_AS, u32::from_le_bytes(rs2_ptr));
139+
let rs1 = exec_state
140+
.vm_read_no_adapter::<u8, INT256_NUM_LIMBS>(RV32_MEMORY_AS, u32::from_le_bytes(rs1_ptr));
141+
let rs2 = exec_state
142+
.vm_read_no_adapter::<u8, INT256_NUM_LIMBS>(RV32_MEMORY_AS, u32::from_le_bytes(rs2_ptr));
143143
let cmp_result = OP::compute(rs1, rs2);
144144
if cmp_result {
145145
pc = (pc as isize + pre_compute.imm) as u32;

‎extensions/bigint/circuit/src/cuda/mod.rs‎

Lines changed: 64 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -35,8 +35,13 @@ use crate::INT256_NUM_BLOCKS;
3535
//////////////////////////////////////////////////////////////////////////////////////
3636
/// ALU
3737
//////////////////////////////////////////////////////////////////////////////////////
38-
pub type BaseAlu256AdapterRecord =
39-
Rv32VecHeapAdapterRecord<2, INT256_NUM_BLOCKS, INT256_NUM_BLOCKS, CONST_BLOCK_SIZE, CONST_BLOCK_SIZE>;
38+
pub type BaseAlu256AdapterRecord = Rv32VecHeapAdapterRecord<
39+
2,
40+
INT256_NUM_BLOCKS,
41+
INT256_NUM_BLOCKS,
42+
CONST_BLOCK_SIZE,
43+
CONST_BLOCK_SIZE,
44+
>;
4045
pub type BaseAlu256CoreRecord = BaseAluCoreRecord<INT256_NUM_LIMBS>;
4146

4247
#[derive(new)]
@@ -57,7 +62,14 @@ impl Chip<DenseRecordArena, GpuBackend> for BaseAlu256ChipGpu {
5762
debug_assert_eq!(records.len() % RECORD_SIZE, 0);
5863

5964
let trace_width = BaseAluCoreCols::<F, INT256_NUM_LIMBS, RV32_CELL_BITS>::width()
60-
+ Rv32VecHeapAdapterCols::<F, 2, INT256_NUM_BLOCKS, INT256_NUM_BLOCKS, CONST_BLOCK_SIZE, CONST_BLOCK_SIZE>::width();
65+
+ Rv32VecHeapAdapterCols::<
66+
F,
67+
2,
68+
INT256_NUM_BLOCKS,
69+
INT256_NUM_BLOCKS,
70+
CONST_BLOCK_SIZE,
71+
CONST_BLOCK_SIZE,
72+
>::width();
6173
let trace_height = next_power_of_two_or_zero(records.len() / RECORD_SIZE);
6274

6375
let d_records = records.to_device().unwrap();
@@ -84,7 +96,8 @@ impl Chip<DenseRecordArena, GpuBackend> for BaseAlu256ChipGpu {
8496
//////////////////////////////////////////////////////////////////////////////////////
8597
/// Branch Equal
8698
//////////////////////////////////////////////////////////////////////////////////////
87-
pub type BranchEqual256AdapterRecord = Rv32VecHeapBranchAdapterRecord<2, INT256_NUM_BLOCKS, CONST_BLOCK_SIZE>;
99+
pub type BranchEqual256AdapterRecord =
100+
Rv32VecHeapBranchAdapterRecord<2, INT256_NUM_BLOCKS, CONST_BLOCK_SIZE>;
88101
pub type BranchEqual256CoreRecord = BranchEqualCoreRecord<INT256_NUM_LIMBS>;
89102

90103
#[derive(new)]
@@ -133,8 +146,13 @@ impl Chip<DenseRecordArena, GpuBackend> for BranchEqual256ChipGpu {
133146
//////////////////////////////////////////////////////////////////////////////////////
134147
/// Less Than
135148
//////////////////////////////////////////////////////////////////////////////////////
136-
pub type LessThan256AdapterRecord =
137-
Rv32VecHeapAdapterRecord<2, INT256_NUM_BLOCKS, INT256_NUM_BLOCKS, CONST_BLOCK_SIZE, CONST_BLOCK_SIZE>;
149+
pub type LessThan256AdapterRecord = Rv32VecHeapAdapterRecord<
150+
2,
151+
INT256_NUM_BLOCKS,
152+
INT256_NUM_BLOCKS,
153+
CONST_BLOCK_SIZE,
154+
CONST_BLOCK_SIZE,
155+
>;
138156
pub type LessThan256CoreRecord = LessThanCoreRecord<INT256_NUM_LIMBS, RV32_CELL_BITS>;
139157

140158
#[derive(new)]
@@ -155,7 +173,14 @@ impl Chip<DenseRecordArena, GpuBackend> for LessThan256ChipGpu {
155173
debug_assert_eq!(records.len() % RECORD_SIZE, 0);
156174

157175
let trace_width = LessThanCoreCols::<F, INT256_NUM_LIMBS, RV32_CELL_BITS>::width()
158-
+ Rv32VecHeapAdapterCols::<F, 2, INT256_NUM_BLOCKS, INT256_NUM_BLOCKS, CONST_BLOCK_SIZE, CONST_BLOCK_SIZE>::width();
176+
+ Rv32VecHeapAdapterCols::<
177+
F,
178+
2,
179+
INT256_NUM_BLOCKS,
180+
INT256_NUM_BLOCKS,
181+
CONST_BLOCK_SIZE,
182+
CONST_BLOCK_SIZE,
183+
>::width();
159184
let trace_height = next_power_of_two_or_zero(records.len() / RECORD_SIZE);
160185

161186
let d_records = records.to_device().unwrap();
@@ -182,7 +207,8 @@ impl Chip<DenseRecordArena, GpuBackend> for LessThan256ChipGpu {
182207
//////////////////////////////////////////////////////////////////////////////////////
183208
/// Branch Less Than
184209
//////////////////////////////////////////////////////////////////////////////////////
185-
pub type BranchLessThan256AdapterRecord = Rv32VecHeapBranchAdapterRecord<2, INT256_NUM_BLOCKS, CONST_BLOCK_SIZE>;
210+
pub type BranchLessThan256AdapterRecord =
211+
Rv32VecHeapBranchAdapterRecord<2, INT256_NUM_BLOCKS, CONST_BLOCK_SIZE>;
186212
pub type BranchLessThan256CoreRecord = BranchLessThanCoreRecord<INT256_NUM_LIMBS, RV32_CELL_BITS>;
187213

188214
#[derive(new)]
@@ -231,8 +257,13 @@ impl Chip<DenseRecordArena, GpuBackend> for BranchLessThan256ChipGpu {
231257
//////////////////////////////////////////////////////////////////////////////////////
232258
/// Shift
233259
//////////////////////////////////////////////////////////////////////////////////////
234-
pub type Shift256AdapterRecord =
235-
Rv32VecHeapAdapterRecord<2, INT256_NUM_BLOCKS, INT256_NUM_BLOCKS, CONST_BLOCK_SIZE, CONST_BLOCK_SIZE>;
260+
pub type Shift256AdapterRecord = Rv32VecHeapAdapterRecord<
261+
2,
262+
INT256_NUM_BLOCKS,
263+
INT256_NUM_BLOCKS,
264+
CONST_BLOCK_SIZE,
265+
CONST_BLOCK_SIZE,
266+
>;
236267
pub type Shift256CoreRecord = ShiftCoreRecord<INT256_NUM_LIMBS, RV32_CELL_BITS>;
237268

238269
#[derive(new)]
@@ -253,7 +284,14 @@ impl Chip<DenseRecordArena, GpuBackend> for Shift256ChipGpu {
253284
debug_assert_eq!(records.len() % RECORD_SIZE, 0);
254285

255286
let trace_width = ShiftCoreCols::<F, INT256_NUM_LIMBS, RV32_CELL_BITS>::width()
256-
+ Rv32VecHeapAdapterCols::<F, 2, INT256_NUM_BLOCKS, INT256_NUM_BLOCKS, CONST_BLOCK_SIZE, CONST_BLOCK_SIZE>::width();
287+
+ Rv32VecHeapAdapterCols::<
288+
F,
289+
2,
290+
INT256_NUM_BLOCKS,
291+
INT256_NUM_BLOCKS,
292+
CONST_BLOCK_SIZE,
293+
CONST_BLOCK_SIZE,
294+
>::width();
257295
let trace_height = next_power_of_two_or_zero(records.len() / RECORD_SIZE);
258296

259297
let d_records = records.to_device().unwrap();
@@ -280,8 +318,13 @@ impl Chip<DenseRecordArena, GpuBackend> for Shift256ChipGpu {
280318
//////////////////////////////////////////////////////////////////////////////////////
281319
/// Multiplication
282320
//////////////////////////////////////////////////////////////////////////////////////
283-
pub type Multiplication256AdapterRecord =
284-
Rv32VecHeapAdapterRecord<2, INT256_NUM_BLOCKS, INT256_NUM_BLOCKS, CONST_BLOCK_SIZE, CONST_BLOCK_SIZE>;
321+
pub type Multiplication256AdapterRecord = Rv32VecHeapAdapterRecord<
322+
2,
323+
INT256_NUM_BLOCKS,
324+
INT256_NUM_BLOCKS,
325+
CONST_BLOCK_SIZE,
326+
CONST_BLOCK_SIZE,
327+
>;
285328
pub type Multiplication256CoreRecord = MultiplicationCoreRecord<INT256_NUM_LIMBS, RV32_CELL_BITS>;
286329

287330
#[derive(new)]
@@ -304,7 +347,14 @@ impl Chip<DenseRecordArena, GpuBackend> for Multiplication256ChipGpu {
304347
debug_assert_eq!(records.len() % RECORD_SIZE, 0);
305348

306349
let trace_width = MultiplicationCoreCols::<F, INT256_NUM_LIMBS, RV32_CELL_BITS>::width()
307-
+ Rv32VecHeapAdapterCols::<F, 2, INT256_NUM_BLOCKS, INT256_NUM_BLOCKS, CONST_BLOCK_SIZE, CONST_BLOCK_SIZE>::width();
350+
+ Rv32VecHeapAdapterCols::<
351+
F,
352+
2,
353+
INT256_NUM_BLOCKS,
354+
INT256_NUM_BLOCKS,
355+
CONST_BLOCK_SIZE,
356+
CONST_BLOCK_SIZE,
357+
>::width();
308358
let trace_height = next_power_of_two_or_zero(records.len() / RECORD_SIZE);
309359

310360
let d_records = records.to_device().unwrap();

‎extensions/bigint/circuit/src/extension/mod.rs‎

Lines changed: 30 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -14,10 +14,6 @@ use openvm_circuit::{
1414
},
1515
system::{memory::SharedMemoryHelper, SystemChipInventory, SystemCpuBuilder, SystemPort},
1616
};
17-
use openvm_rv32_adapters::{
18-
Rv32VecHeapAdapterAir, Rv32VecHeapAdapterExecutor, Rv32VecHeapAdapterFiller,
19-
Rv32VecHeapBranchAdapterAir, Rv32VecHeapBranchAdapterExecutor, Rv32VecHeapBranchAdapterFiller,
20-
};
2117
use openvm_circuit_derive::{AnyEnum, Executor, MeteredExecutor, PreflightExecutor};
2218
use openvm_circuit_primitives::{
2319
bitwise_op_lookup::{
@@ -30,6 +26,10 @@ use openvm_circuit_primitives::{
3026
},
3127
};
3228
use openvm_instructions::{program::DEFAULT_PC_STEP, LocalOpcode};
29+
use openvm_rv32_adapters::{
30+
Rv32VecHeapAdapterAir, Rv32VecHeapAdapterExecutor, Rv32VecHeapAdapterFiller,
31+
Rv32VecHeapBranchAdapterAir, Rv32VecHeapBranchAdapterExecutor, Rv32VecHeapBranchAdapterFiller,
32+
};
3333
use openvm_rv32im_circuit::Rv32ImCpuProverExt;
3434
use openvm_stark_backend::{
3535
config::{StarkGenericConfig, Val},
@@ -234,7 +234,9 @@ impl<SC: StarkGenericConfig> VmCircuitExtension<SC> for Int256 {
234234
INT256_NUM_BLOCKS,
235235
CONST_BLOCK_SIZE,
236236
CONST_BLOCK_SIZE,
237-
>::new(exec_bridge, memory_bridge, bitwise_lu, pointer_max_bits)),
237+
>::new(
238+
exec_bridge, memory_bridge, bitwise_lu, pointer_max_bits
239+
)),
238240
BaseAluCoreAir::new(bitwise_lu, Rv32BaseAlu256Opcode::CLASS_OFFSET),
239241
);
240242
inventory.add_air(alu);
@@ -246,7 +248,9 @@ impl<SC: StarkGenericConfig> VmCircuitExtension<SC> for Int256 {
246248
INT256_NUM_BLOCKS,
247249
CONST_BLOCK_SIZE,
248250
CONST_BLOCK_SIZE,
249-
>::new(exec_bridge, memory_bridge, bitwise_lu, pointer_max_bits)),
251+
>::new(
252+
exec_bridge, memory_bridge, bitwise_lu, pointer_max_bits
253+
)),
250254
LessThanCoreAir::new(bitwise_lu, Rv32LessThan256Opcode::CLASS_OFFSET),
251255
);
252256
inventory.add_air(lt);
@@ -256,7 +260,9 @@ impl<SC: StarkGenericConfig> VmCircuitExtension<SC> for Int256 {
256260
2,
257261
INT256_NUM_BLOCKS,
258262
CONST_BLOCK_SIZE,
259-
>::new(exec_bridge, memory_bridge, bitwise_lu, pointer_max_bits)),
263+
>::new(
264+
exec_bridge, memory_bridge, bitwise_lu, pointer_max_bits
265+
)),
260266
BranchEqualCoreAir::new(Rv32BranchEqual256Opcode::CLASS_OFFSET, DEFAULT_PC_STEP),
261267
);
262268
inventory.add_air(beq);
@@ -266,7 +272,9 @@ impl<SC: StarkGenericConfig> VmCircuitExtension<SC> for Int256 {
266272
2,
267273
INT256_NUM_BLOCKS,
268274
CONST_BLOCK_SIZE,
269-
>::new(exec_bridge, memory_bridge, bitwise_lu, pointer_max_bits)),
275+
>::new(
276+
exec_bridge, memory_bridge, bitwise_lu, pointer_max_bits
277+
)),
270278
BranchLessThanCoreAir::new(bitwise_lu, Rv32BranchLessThan256Opcode::CLASS_OFFSET),
271279
);
272280
inventory.add_air(blt);
@@ -278,7 +286,9 @@ impl<SC: StarkGenericConfig> VmCircuitExtension<SC> for Int256 {
278286
INT256_NUM_BLOCKS,
279287
CONST_BLOCK_SIZE,
280288
CONST_BLOCK_SIZE,
281-
>::new(exec_bridge, memory_bridge, bitwise_lu, pointer_max_bits)),
289+
>::new(
290+
exec_bridge, memory_bridge, bitwise_lu, pointer_max_bits
291+
)),
282292
MultiplicationCoreAir::new(range_tuple_checker, Rv32Mul256Opcode::CLASS_OFFSET),
283293
);
284294
inventory.add_air(mult);
@@ -290,7 +300,9 @@ impl<SC: StarkGenericConfig> VmCircuitExtension<SC> for Int256 {
290300
INT256_NUM_BLOCKS,
291301
CONST_BLOCK_SIZE,
292302
CONST_BLOCK_SIZE,
293-
>::new(exec_bridge, memory_bridge, bitwise_lu, pointer_max_bits)),
303+
>::new(
304+
exec_bridge, memory_bridge, bitwise_lu, pointer_max_bits
305+
)),
294306
ShiftCoreAir::new(bitwise_lu, range_checker, Rv32Shift256Opcode::CLASS_OFFSET),
295307
);
296308
inventory.add_air(shift);
@@ -387,11 +399,10 @@ where
387399
inventory.next_air::<Rv32BranchEqual256Air>()?;
388400
let beq = Rv32BranchEqual256Chip::new(
389401
BranchEqualFiller::new(
390-
Rv32VecHeapBranchAdapterFiller::<
391-
2,
392-
INT256_NUM_BLOCKS,
393-
CONST_BLOCK_SIZE,
394-
>::new(pointer_max_bits, bitwise_lu.clone()),
402+
Rv32VecHeapBranchAdapterFiller::<2, INT256_NUM_BLOCKS, CONST_BLOCK_SIZE>::new(
403+
pointer_max_bits,
404+
bitwise_lu.clone(),
405+
),
395406
Rv32BranchEqual256Opcode::CLASS_OFFSET,
396407
DEFAULT_PC_STEP,
397408
),
@@ -402,11 +413,10 @@ where
402413
inventory.next_air::<Rv32BranchLessThan256Air>()?;
403414
let blt = Rv32BranchLessThan256Chip::new(
404415
BranchLessThanFiller::new(
405-
Rv32VecHeapBranchAdapterFiller::<
406-
2,
407-
INT256_NUM_BLOCKS,
408-
CONST_BLOCK_SIZE,
409-
>::new(pointer_max_bits, bitwise_lu.clone()),
416+
Rv32VecHeapBranchAdapterFiller::<2, INT256_NUM_BLOCKS, CONST_BLOCK_SIZE>::new(
417+
pointer_max_bits,
418+
bitwise_lu.clone(),
419+
),
410420
bitwise_lu.clone(),
411421
Rv32BranchLessThan256Opcode::CLASS_OFFSET,
412422
),

‎extensions/bigint/circuit/src/less_than.rs‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -131,10 +131,10 @@ unsafe fn execute_e12_impl<F: PrimeField32, CTX: ExecutionCtxTrait, const IS_U25
131131
let rs1_ptr = exec_state.vm_read_no_adapter::<u8, 4>(RV32_REGISTER_AS, pre_compute.b as u32);
132132
let rs2_ptr = exec_state.vm_read_no_adapter::<u8, 4>(RV32_REGISTER_AS, pre_compute.c as u32);
133133
let rd_ptr = exec_state.vm_read_no_adapter::<u8, 4>(RV32_REGISTER_AS, pre_compute.a as u32);
134-
let rs1 =
135-
exec_state.vm_read_no_adapter::<u8, INT256_NUM_LIMBS>(RV32_MEMORY_AS, u32::from_le_bytes(rs1_ptr));
136-
let rs2 =
137-
exec_state.vm_read_no_adapter::<u8, INT256_NUM_LIMBS>(RV32_MEMORY_AS, u32::from_le_bytes(rs2_ptr));
134+
let rs1 = exec_state
135+
.vm_read_no_adapter::<u8, INT256_NUM_LIMBS>(RV32_MEMORY_AS, u32::from_le_bytes(rs1_ptr));
136+
let rs2 = exec_state
137+
.vm_read_no_adapter::<u8, INT256_NUM_LIMBS>(RV32_MEMORY_AS, u32::from_le_bytes(rs2_ptr));
138138
let cmp_result = if IS_U256 {
139139
common::u256_lt(rs1, rs2)
140140
} else {

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