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Copy file name to clipboardExpand all lines: extensions/sha2/circuit/README.md
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# SHA256 VM Extension
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# SHA-2 VM Extension
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This crate contains the circuit for the SHA256 VM extension.
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This crate contains circuits for the SHA-2 family of hash functions.
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We support SHA-256, SHA-512, and SHA-384.
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## SHA-256 Algorithm Summary
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## SHA-2 Algorithms Summary
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See the [FIPS standard](https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.180-4.pdf), in particular, section 6.2 for reference.
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The SHA-256, SHA-512, and SHA-384 algorithms are similar in structure.
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We will first describe the SHA-256 algorithm, and then describe the differences between the three algorithms.
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See the [FIPS standard](https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.180-4.pdf) for reference. In particular, sections 6.2, 6.4, and 6.5.
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In short the SHA-256 algorithm works as follows.
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1. Pad the message to 512 bits and split it into 512-bit 'blocks'.
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2. Initialize a hash state consisting of eight 32-bit words.
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2. Initialize a hash state consisting of eight 32-bit words to a specific constant value.
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3. For each block,
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1. split the message into 16 32-bit words and produce 48 more 'message schedule' words based on them.
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2. apply 64 'rounds' to update the hash state based on the message schedule.
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3. add the previous block's final hash state to the current hash state (modulo `2^32`).
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1. split the message into 16 32-bit words and produce 48 more words based on them. The 16 message words together with the 48 additional words are called the 'message schedule'.
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2. apply a scrambling function 64 times to the hash state to update it based on the message schedule. We call each update a 'round'.
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3. add the previous block's final hash state to the current hash state (modulo $2^{32}$).
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4. The output is the final hash state
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The differences with the SHA-512 algorithm are that:
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- SHA-512 uses 64-bit words, 1024-bit blocks, performs 80 rounds, and produces a 512-bit output.
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- all the arithmetic is done modulo $2^{64}$.
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- the initial hash state is different.
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The SHA-384 algorithm is a truncation of the SHA-512 output to 384 bits, and the only difference is that the initial hash state is different.
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## Design Overview
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This chip produces an AIR that consists of 17 rows for each block (512 bits) in the message, and no more rows.
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The first 16 rows of each block are called 'round rows', and each of them represents four rounds of the SHA-256 algorithm.
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Each row constrains updates to the working variables on each round, and it also constrains the message schedule words based on previous rounds.
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The final row is called a 'digest row' and it produces a final hash for the block, computed as the sum of the working variables and the previous block's final hash.
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We reuse the same AIR code to produce circuits for all three algorithms.
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To achieve this, we parameterize the AIR by constants (such as the word size, number of rounds, and block size) that are specific to each algorithm.
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This chip produces an AIR that consists of $R+1$ rows for each block of the message, and no more rows
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(for SHA-256, $R = 16$ and for SHA-512 and SHA-384, $R = 20$).
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The first $R$ rows of each block are called 'round rows', and each of them constrains four rounds of the hash algorithm.
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Each row constrains updates to the working variables on each round, and also constrains the message schedule words based on previous rounds.
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The final row of each block is called a 'digest row' and it produces a final hash for the block, computed as the sum of the working variables and the previous block's final hash.
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Note that this chip only supports messages of length less than `2^29` bytes.
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Note that this chip only supports messages of length less than $2^{29}$ bytes.
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### Storing working variables
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The last block of every message should have the `is_last_block` flag set to `1`.
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Note that `is_last_block` is not constrained to be true for the last block of every message, instead it *defines* what the last block of a message is.
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For instance, if we produce an air with 10 blocks and only the last block has `is_last_block = 1` then the constraints will interpret it as a single message of length 10 blocks.
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For instance, if we produce a trace with 10 blocks and only the last block has `is_last_block = 1` then the constraints will interpret it as a single message of length 10 blocks.
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If, however, we set `is_last_block` to true for the 6th block, the trace will be interpreted as hashing two messages, each of length 5 blocks.
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Note that we do constrain, however, that the very last block of the trace has `is_last_block = 1`.
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### Block index counter variables
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There are two "block index" counter variables in each row of the air named `global_block_idx` and `local_block_idx`.
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Both of these variables take on the same value on all 17 rows in a block.
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There are two "block index" counter variables in each row named `global_block_idx` and `local_block_idx`.
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Both of these variables take on the same value on all $R+1$ rows in a block.
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The `global_block_idx` is the index of the block in the entire trace.
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The very first 17 rows in the trace will have `global_block_idx = 1` and the counter will increment by 1 between blocks.
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The very first block in the trace will have `global_block_idx = 1` on each row and the counter will increment by 1 between blocks.
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The padding rows will all have `global_block_idx = 0`.
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The `global_block_idx` is used in interaction constraints to constrain the value of `hash` between blocks.
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### VM air vs SubAir
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The SHA-256 VM extension chip uses the `Sha256Air` SubAir to help constrain the SHA-256 hash.
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The VM extension air constrains the correctness of the SHA message padding, while the SubAir adds all other constraints related to the hash algorithm.
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The VM extension air also constrains memory reads and writes.
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The SHA-2 VM extension chip uses the `Sha2Air` SubAir to help constrain the appropriate SHA-2 hash algorithm.
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The SubAir is also parameterized by the specific SHA-2 variant's constants.
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The VM extension AIR constrains the correctness of the message padding, while the SubAir adds all other constraints related to the hash algorithm.
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The VM extension AIR also constrains memory reads and writes.
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### A gotcha about padding rows
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There are two senses of the word padding used in the context of this chip and this can be confusing.
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First, we use padding to refer to the extra bits added to the message that is input to the SHA-256 algorithm in order to make the input's length a multiple of 512 bits.
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So, we may use the term 'padding rows' to refer to round rows that correspond to the padded bits of a message (as in `Sha256VmAir::eval_padding_row`).
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First, we use padding to refer to the extra bits added to the message that is input to the hash algorithm in order to make the input's length a multiple of the block size.
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So, we may use the term 'padding rows' to refer to round rows that correspond to the padded bits of a message (as in `Sha2VmAir::eval_padding_row`).
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Second, the dummy rows that are added to the trace to make the trace height a power of 2 are also called padding rows (see the `is_padding_row` flag).
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In the SubAir, padding row probably means dummy row.
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In the VM air, it probably refers to SHA-256 padding.
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In the VM air, it probably refers to the message padding.
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