fix: several typos of different importance (#1627)

I know you don't acknowledge PR's with minor typo fixes, 

But I found some typos that should be fixed, and they are not subjective
or minor ones.

Author: crStiv

audits/v1-internal/extension-algebra.md

@@ -29,7 +29,7 @@ These should fail to verify, but they currently pass.
 
 **Recommendation:** 
 On setup rows, add the constraints `c_lt_mark = 2` and `sum_i lt_marker[i] = 2`.
-This (together with the existing contsraints) will ensure `lt_marker` has one 2 and that the remaining entries are 0s.
+This (together with the existing constraints) will ensure `lt_marker` has one 2 and that the remaining entries are 0s.
 Then modify the `b[i] = N[i]` constraint to constrain `b[i] = N[i]` when `prefix_sum` is not 1 or `final_sum - is_setup` (currently it applies the constraint when `prefix_sum` is not 1 or `final_sum`).
 On setup rows, `final_sum - is_setup = 2 - 1 = 1` and `prefix_sum` is 0 or 2 for all `i` so `b[i] = N[i]` will be constrained for all `i`.
 See the [soundness proof](#31-soundness-of-is_eq-chip) below for more details.

audits/v1-internal/extension-native.md

@@ -37,7 +37,7 @@ Add the following constraints to `NativePoseidon2Air`:
 **Resolution:** https://github.com/openvm-org/openvm/pull/1435
 https://github.com/openvm-org/openvm/commit/d768af4de1500044a49ab642915174e83eb86bcb
 
-### 2.2 NativePosiedon2Air constraints allow padding rows with `is_exhausted` cells
+### 2.2 NativePoseidon2Air constraints allow padding rows with `is_exhausted` cells
 
 **Severity:** Medium
 **Context:** https://github.com/openvm-org/openvm/blob/830053d599606fd5c7dc8f8346710f9d6854beae/extensions/native/circuit/src/poseidon2/air.rs
@@ -50,7 +50,7 @@ However, all the attacker can do is effectively repeatedly apply the Poseidon2
 permutation to the final hash, which is unlikely to be useful in an attack.
 
 **Recommendation:**
-Add a constraint that `is_exhausted[0] = 0` or simply remove the `is_exhasted[0]` variable.
+Add a constraint that `is_exhausted[0] = 0` or simply remove the `is_exhausted[0]` variable.
 
 **Resolution:** https://github.com/openvm-org/openvm/pull/1436
 https://github.com/openvm-org/openvm/commit/2514e5d371d5706d22f573746213cd062eea4142
@@ -230,7 +230,7 @@ https://github.com/openvm-org/openvm/commit/960abb0b9edb8ef8bca3d62054a20fb3edf3
 ## 3. Discussion
 
 This review included all chips under `native/circuit/src` as well as
-`native/tranpsiler`.
+`native/transpiler`.
 
 Aside from the issues found above, one observation from reviewing the AIRs is
 that the AIRs are not always consistent with whether or not they enforce if an

audits/v1-internal/isa.md

@@ -19,7 +19,7 @@ Findings include anything that could warrant change or unexpected behavior that
 
 **Context:** [link](https://cantina.xyz/code/c486d600-bed0-4fc6-aed1-de759fd29fa2/openvm/extensions/rv32im/circuit/src/adapters/loadstore.rs#L183)
 
-**Description:** `Rv32LoadStoreChip` chip doesn't assert supoprted address spaces. An valid instruction could read from an address space which requires elements larger than 1 byte or write into an address space which requires elements smaller than 1 byte. This could break address space invariants which other chips take.
+**Description:** `Rv32LoadStoreChip` chip doesn't assert supported address spaces. An valid instruction could read from an address space which requires elements larger than 1 byte or write into an address space which requires elements smaller than 1 byte. This could break address space invariants which other chips take.
 
 This could only happen when users intend to add some invalid instruction.