From a367d7a2cf9d0ea12a5a1261b42b8ce605701d5d Mon Sep 17 00:00:00 2001 From: 21km43 Date: Mon, 9 Sep 2024 14:53:38 +0900 Subject: [PATCH 01/20] USB PD: Improve requesting fixed voltage function --- .../usbpd_sink_request_voltage.ino | 5 ++++- libraries/USBPD_SINK/src/usbpd_sink.c | 7 ++++--- libraries/USBPD_SINK/src/usbpd_sink.h | 3 ++- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/libraries/USBPD_SINK/examples/usbpd_sink_request_voltage/usbpd_sink_request_voltage.ino b/libraries/USBPD_SINK/examples/usbpd_sink_request_voltage/usbpd_sink_request_voltage.ino index 6193386d..d9d82ab2 100644 --- a/libraries/USBPD_SINK/examples/usbpd_sink_request_voltage/usbpd_sink_request_voltage.ino +++ b/libraries/USBPD_SINK/examples/usbpd_sink_request_voltage/usbpd_sink_request_voltage.ino @@ -20,7 +20,10 @@ void loop() { if(usbpd_sink_get_ready()) { - usbpd_sink_set_request_fixed_voltage(setVoltage); + if(usbpd_sink_set_request_fixed_voltage(setVoltage) == false) + { + Serial.printf("unsupported voltage\r\n"); + } } // button, myIndex++ diff --git a/libraries/USBPD_SINK/src/usbpd_sink.c b/libraries/USBPD_SINK/src/usbpd_sink.c index 0292e38b..82f166b1 100644 --- a/libraries/USBPD_SINK/src/usbpd_sink.c +++ b/libraries/USBPD_SINK/src/usbpd_sink.c @@ -38,7 +38,7 @@ void usbpd_sink_clear_ready(void) pdControl_g.cc_USBPD_READY = 0; } -void usbpd_sink_set_request_fixed_voltage(Request_voltage_t requestVoltage) +bool usbpd_sink_set_request_fixed_voltage(Request_voltage_t requestVoltage) { uint16_t targetVoltage; switch (requestVoltage) @@ -73,11 +73,12 @@ void usbpd_sink_set_request_fixed_voltage(Request_voltage_t requestVoltage) if(pdControl_g.cc_FixedSourceCap[i].Voltage == targetVoltage) { pdControl_g.cc_SetPDONum = i+1; - return; + return true; } } - pdControl_g.cc_SetPDONum = (pdControl_g.cc_SourcePDONum - pdControl_g.cc_SourcePPSNum); + // unsupported voltage + return false; } void timer3_init(uint16_t arr, uint16_t psc) diff --git a/libraries/USBPD_SINK/src/usbpd_sink.h b/libraries/USBPD_SINK/src/usbpd_sink.h index 1672d048..12dcc278 100644 --- a/libraries/USBPD_SINK/src/usbpd_sink.h +++ b/libraries/USBPD_SINK/src/usbpd_sink.h @@ -5,6 +5,7 @@ extern "C" { #endif /* end of __cplusplus */ +#include #include "usbpd_def.h" // Register Bit Definition @@ -201,7 +202,7 @@ void usbpd_sink_process(void); uint8_t usbpd_sink_get_ready(void); void usbpd_sink_clear_ready(void); -void usbpd_sink_set_request_fixed_voltage(Request_voltage_t requestVoltage); +bool usbpd_sink_set_request_fixed_voltage(Request_voltage_t requestVoltage); #ifdef __cplusplus From 681a2908f4a330ef45bbdc1cd5089b80bf5cbd6f Mon Sep 17 00:00:00 2001 From: 21km43 <21km43@gmail.com> Date: Mon, 9 Sep 2024 19:09:08 +0900 Subject: [PATCH 02/20] add usb support for ch32l103 --- boards.txt | 6 ++++++ tools/makeboards.py | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/boards.txt b/boards.txt index 73d4c4ca..8a3ed40b 100644 --- a/boards.txt +++ b/boards.txt @@ -781,6 +781,12 @@ CH32L10x_EVT.menu.pnum.CH32L103C8T6.build.IQ_math_RV32= CH32L10x_EVT.menu.pnum.CH32L103C8T6.build.ch_extra_lib=-lprintf +# USB support +CH32L10x_EVT.menu.usb.none=None +CH32L10x_EVT.menu.usb.none.build.usb_flags= +CH32L10x_EVT.menu.usb.tinyusb_usbd=Adafruit TinyUSB with USBD +CH32L10x_EVT.menu.usb.tinyusb_usbd.build.usb_flags=-DUSBCON -DUSE_TINYUSB -DCFG_TUD_WCH_USBIP_FSDEV=1 "-I{runtime.platform.path}/libraries/Adafruit_TinyUSB_Arduino/src/arduino" + # Upload menu CH32L10x_EVT.menu.upload_method.swdMethod=WCH-SWD CH32L10x_EVT.menu.upload_method.swdMethod.upload.protocol= diff --git a/tools/makeboards.py b/tools/makeboards.py index 40c0abd8..d8b0aff3 100644 --- a/tools/makeboards.py +++ b/tools/makeboards.py @@ -95,7 +95,7 @@ 'CH32L10x': { 'name': 'CH32L10x_EVT', 'info': '-lprintf', - 'usb': [], + 'usb': ['tinyusb_usbd'], 'hsi': [96, 72, 56, 48, 0, 'HSI_LP'], 'hse': [96, 72, 56, 48, 0], 'pnums': { From b32e6b6d3d43f06477ee6d43593670b45c8bff8f Mon Sep 17 00:00:00 2001 From: 21km43 <21km43@gmail.com> Date: Mon, 9 Sep 2024 19:09:42 +0900 Subject: [PATCH 03/20] include "Adafruit_TinyUSB.h" if defined USE_TINYUSB --- cores/arduino/WSerial.h | 1 + 1 file changed, 1 insertion(+) diff --git a/cores/arduino/WSerial.h b/cores/arduino/WSerial.h index 874fb3c8..ee01214c 100644 --- a/cores/arduino/WSerial.h +++ b/cores/arduino/WSerial.h @@ -6,6 +6,7 @@ #if defined(USE_TINYUSB) #include "Adafruit_USBD_CDC.h" +#include "Adafruit_TinyUSB.h" #define Serial SerialTinyUSB #endif From 900e3b4288c2bb7b1921101fcc1063ab5dbeda65 Mon Sep 17 00:00:00 2001 From: 21km43 <21km43@gmail.com> Date: Mon, 9 Sep 2024 23:05:30 +0900 Subject: [PATCH 04/20] usb support fix --- tools/makeboards.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/makeboards.py b/tools/makeboards.py index d8b0aff3..b75ef04b 100644 --- a/tools/makeboards.py +++ b/tools/makeboards.py @@ -51,7 +51,7 @@ 'CH32X035': { 'name': 'CH32X035_EVT', 'info': '', - 'usb': [], + 'usb': ['tinyusb_usbfs'], 'hsi': [48, 24, 16, 12, 8], 'hse': [], 'pnums': { @@ -95,7 +95,7 @@ 'CH32L10x': { 'name': 'CH32L10x_EVT', 'info': '-lprintf', - 'usb': ['tinyusb_usbd'], + 'usb': ['tinyusb_usbfs'], 'hsi': [96, 72, 56, 48, 0, 'HSI_LP'], 'hse': [96, 72, 56, 48, 0], 'pnums': { From 1fc731b6c3d688d128380cf9a39333122c00c6d4 Mon Sep 17 00:00:00 2001 From: 21km43 <21km43@gmail.com> Date: Tue, 10 Sep 2024 10:34:36 +0900 Subject: [PATCH 05/20] remove include file --- cores/arduino/WSerial.h | 1 - 1 file changed, 1 deletion(-) diff --git a/cores/arduino/WSerial.h b/cores/arduino/WSerial.h index ee01214c..874fb3c8 100644 --- a/cores/arduino/WSerial.h +++ b/cores/arduino/WSerial.h @@ -6,7 +6,6 @@ #if defined(USE_TINYUSB) #include "Adafruit_USBD_CDC.h" -#include "Adafruit_TinyUSB.h" #define Serial SerialTinyUSB #endif From 4c1c6e70ed99d51e33c3a645acb18230abfc8af2 Mon Sep 17 00:00:00 2001 From: 21km43 <21km43@gmail.com> Date: Tue, 10 Sep 2024 10:37:10 +0900 Subject: [PATCH 06/20] board.txt fix --- boards.txt | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/boards.txt b/boards.txt index 8a3ed40b..7ae8f973 100644 --- a/boards.txt +++ b/boards.txt @@ -251,6 +251,12 @@ CH32X035_EVT.menu.pnum.CH32X035G8U.build.IQ_math_RV32= CH32X035_EVT.menu.pnum.CH32X035G8U.build.ch_extra_lib=-lprintf +# USB support +CH32X035_EVT.menu.usb.none=None +CH32X035_EVT.menu.usb.none.build.usb_flags= +CH32X035_EVT.menu.usb.tinyusb_usbfs=Adafruit TinyUSB with USBFS +CH32X035_EVT.menu.usb.tinyusb_usbfs.build.usb_flags=-DUSBCON -DUSE_TINYUSB -DCFG_TUD_WCH_USBIP_USBFS=1 "-I{runtime.platform.path}/libraries/Adafruit_TinyUSB_Arduino/src/arduino" + # Upload menu CH32X035_EVT.menu.upload_method.swdMethod=WCH-SWD CH32X035_EVT.menu.upload_method.swdMethod.upload.protocol= @@ -784,8 +790,8 @@ CH32L10x_EVT.menu.pnum.CH32L103C8T6.build.ch_extra_lib=-lprintf # USB support CH32L10x_EVT.menu.usb.none=None CH32L10x_EVT.menu.usb.none.build.usb_flags= -CH32L10x_EVT.menu.usb.tinyusb_usbd=Adafruit TinyUSB with USBD -CH32L10x_EVT.menu.usb.tinyusb_usbd.build.usb_flags=-DUSBCON -DUSE_TINYUSB -DCFG_TUD_WCH_USBIP_FSDEV=1 "-I{runtime.platform.path}/libraries/Adafruit_TinyUSB_Arduino/src/arduino" +CH32L10x_EVT.menu.usb.tinyusb_usbfs=Adafruit TinyUSB with USBFS +CH32L10x_EVT.menu.usb.tinyusb_usbfs.build.usb_flags=-DUSBCON -DUSE_TINYUSB -DCFG_TUD_WCH_USBIP_USBFS=1 "-I{runtime.platform.path}/libraries/Adafruit_TinyUSB_Arduino/src/arduino" # Upload menu CH32L10x_EVT.menu.upload_method.swdMethod=WCH-SWD From fbb63b04be77961d49e3eb10aaffb229aff8a91f Mon Sep 17 00:00:00 2001 From: 21km43 <21km43@gmail.com> Date: Tue, 10 Sep 2024 10:38:31 +0900 Subject: [PATCH 07/20] submodule update --- libraries/Adafruit_TinyUSB_Arduino | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/Adafruit_TinyUSB_Arduino b/libraries/Adafruit_TinyUSB_Arduino index 1f9da491..05686e7f 160000 --- a/libraries/Adafruit_TinyUSB_Arduino +++ b/libraries/Adafruit_TinyUSB_Arduino @@ -1 +1 @@ -Subproject commit 1f9da4918f2c05441a9bfc3866a5b9cc03f2da62 +Subproject commit 05686e7f97de299487fc2291864591d0a18d9bb6 From 519cd7dd8702f6f7156a2f937bae567c502b8234 Mon Sep 17 00:00:00 2001 From: 21km43 <21km43@gmail.com> Date: Tue, 10 Sep 2024 14:58:20 +0900 Subject: [PATCH 08/20] remove ch32x035 usb support --- boards.txt | 6 ------ tools/makeboards.py | 2 +- 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/boards.txt b/boards.txt index 7ae8f973..30fab853 100644 --- a/boards.txt +++ b/boards.txt @@ -251,12 +251,6 @@ CH32X035_EVT.menu.pnum.CH32X035G8U.build.IQ_math_RV32= CH32X035_EVT.menu.pnum.CH32X035G8U.build.ch_extra_lib=-lprintf -# USB support -CH32X035_EVT.menu.usb.none=None -CH32X035_EVT.menu.usb.none.build.usb_flags= -CH32X035_EVT.menu.usb.tinyusb_usbfs=Adafruit TinyUSB with USBFS -CH32X035_EVT.menu.usb.tinyusb_usbfs.build.usb_flags=-DUSBCON -DUSE_TINYUSB -DCFG_TUD_WCH_USBIP_USBFS=1 "-I{runtime.platform.path}/libraries/Adafruit_TinyUSB_Arduino/src/arduino" - # Upload menu CH32X035_EVT.menu.upload_method.swdMethod=WCH-SWD CH32X035_EVT.menu.upload_method.swdMethod.upload.protocol= diff --git a/tools/makeboards.py b/tools/makeboards.py index b75ef04b..ac3c6dbb 100644 --- a/tools/makeboards.py +++ b/tools/makeboards.py @@ -51,7 +51,7 @@ 'CH32X035': { 'name': 'CH32X035_EVT', 'info': '', - 'usb': ['tinyusb_usbfs'], + 'usb': [], 'hsi': [48, 24, 16, 12, 8], 'hse': [], 'pnums': { From 94efd9a2fe9e08eed7d7a4aacd7c05eff44e315a Mon Sep 17 00:00:00 2001 From: 21km43 <21km43@gmail.com> Date: Wed, 11 Sep 2024 23:40:14 +0900 Subject: [PATCH 09/20] typo fix --- system/CH32L10x/SRC/Peripheral/inc/ch32l103_usb.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_usb.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_usb.h index a3689f05..ab47c483 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_usb.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_usb.h @@ -17,10 +17,6 @@ extern "C" { #endif -#ifdef __cplusplus - extern "C" { -#endif - /*******************************************************************************/ /* Header File */ #include "stdint.h" From 80e321104ed6b63906d52275e2c3d0d76bfb83e4 Mon Sep 17 00:00:00 2001 From: Maximilian Gerhardt Date: Wed, 11 Sep 2024 18:31:03 +0200 Subject: [PATCH 10/20] Update PIO builder script --- tools/platformio-build.py | 73 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 68 insertions(+), 5 deletions(-) diff --git a/tools/platformio-build.py b/tools/platformio-build.py index af584f5d..68955409 100644 --- a/tools/platformio-build.py +++ b/tools/platformio-build.py @@ -33,7 +33,10 @@ platform = env.PioPlatform() board = env.BoardConfig() mcu = env.BoardConfig().get("build.mcu") -chip_series: str = board.get("build.series", "")[0:-1].upper() + "x" +if mcu.startswith("ch32x03"): + chip_series: str = board.get("build.series", "").upper() +else: + chip_series: str = board.get("build.series", "")[0:-1].upper() + "x" variant_h = board.get("build.arduino.openwch.variant_h") FRAMEWORK_DIR = platform.get_package_dir("framework-arduino-openwch-ch32") @@ -93,8 +96,11 @@ CPPDEFINES= [ ("ARDUINO", 10808), + ("ARDUINO_ARCH_CH32V"), + ("ARDUINO_ARCH_CH32"), ("VARIANT_H", env.StringifyMacro(variant_h)), - chip_series + chip_series, + "NDEBUG" ], # LIBS is handled in _LIBFLAGS below @@ -123,18 +129,75 @@ SIZEDATAREGEXP=r"^(?:\.data|\.bss|\.noinit)\s+(\d+).*", ) +def configure_usb_flags(cpp_defines): + if any([x in cpp_defines for x in ("PIO_FRAMEWORK_ARDUINO_USBD", "PIO_FRAMEWORK_ARDUINO_USBFS", "PIO_FRAMEWORK_ARDUINO_USBHS")]): + env.Append(CPPPATH=[join( + FRAMEWORK_DIR, "libraries", "Adafruit_TinyUSB_Arduino", "src", "arduino")]) + # automatically build with lib_archive = no to make weak linking work, needed for TinyUSB + env_section = "env:" + env["PIOENV"] + platform.config.set(env_section, "lib_archive", False) + else: + return # nothing to do, bye + if "PIO_FRAMEWORK_ARDUINO_USBD" in cpp_defines: + env.Append(CPPDEFINES=[("CFG_TUD_WCH_USBIP_FSDEV", 1)]) + elif "PIO_FRAMEWORK_ARDUINO_USBFS" in cpp_defines: + env.Append(CPPDEFINES=[("CFG_TUD_WCH_USBIP_USBFS", 1)]) + elif "PIO_FRAMEWORK_ARDUINO_USBHS" in cpp_defines: + env.Append(CPPDEFINES=[("CFG_TUD_WCH_USBIP_USBHS", 1)]) + # in any case, add standard flags + # preferably use USB information from arduino.openwch section, + # but fallback to sensible values derived from other parts otherwise. + usb_pid = board.get("build.arduino.earlephilhower.usb_pid", + board.get("build.hwids", [[0, 0]])[0][1]) + usb_vid = board.get("build.arduino.earlephilhower.usb_vid", + board.get("build.hwids", [[0, 0]])[0][0]) + usb_manufacturer = board.get( + "build.arduino.openwch.usb_manufacturer", board.get("vendor", "WCH")) + usb_product = board.get( + "build.arduino.openwch.usb_product", board.get("name", "CH32V")) + + env.Append(CPPDEFINES=[ + "USBCON", + "USE_TINYUSB", + ("USB_VID", usb_vid), + ("USB_PID", usb_pid), + ("USB_MANUFACTURER", '\\"%s\\"' % usb_manufacturer), + ("USB_PRODUCT", '\\"%s\\"' % usb_product), + ]) + +# +# Process configuration flags +# +cpp_defines = env.Flatten(env.get("CPPDEFINES", [])) +# Ignore TinyUSB automatically if not active without requiring ldf_mode = chain+ +if not any([x in cpp_defines for x in ("PIO_FRAMEWORK_ARDUINO_USBD", "PIO_FRAMEWORK_ARDUINO_USBFS", "PIO_FRAMEWORK_ARDUINO_USBHS")]): + env_section = "env:" + env["PIOENV"] + ignored_libs = platform.config.get(env_section, "lib_ignore", []) + if not "Adafruit TinyUSB Library" in ignored_libs: + ignored_libs.append("Adafruit TinyUSB Library") + platform.config.set(env_section, "lib_ignore", ignored_libs) +else: + # one of those macros was activated. explicitly add it to library dependencies. + env_section = "env:" + env["PIOENV"] + set_libs = platform.config.get(env_section, "lib_deps", []) + if not "Adafruit TinyUSB Library" in set_libs: + set_libs.append("Adafruit TinyUSB Library") + platform.config.set(env_section, "lib_deps", set_libs) + +# configure USB stuff +configure_usb_flags(cpp_defines) + # # Target: Build Core Library # libs = [] -if "build.variant" in board: +variant = board.get("build.arduino.openwch.variant", board.get("build.variant", "")) +if variant != "": variants_dir = join( "$PROJECT_DIR", board.get("build.variants_dir")) if board.get( "build.variants_dir", "") else join(FRAMEWORK_DIR, "variants") - - variant = board.get("build.arduino.openwch.variant", board.get("build.variant")) env.Append( CPPPATH=[ join(variants_dir, variant) From c0ff3fa9711c7c7f6c4808fe7c8ccea9d3129901 Mon Sep 17 00:00:00 2001 From: Maximilian Gerhardt Date: Wed, 11 Sep 2024 19:32:43 +0200 Subject: [PATCH 11/20] Access proper subfields --- tools/platformio-build.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/platformio-build.py b/tools/platformio-build.py index 68955409..4b69f1ff 100644 --- a/tools/platformio-build.py +++ b/tools/platformio-build.py @@ -147,9 +147,9 @@ def configure_usb_flags(cpp_defines): # in any case, add standard flags # preferably use USB information from arduino.openwch section, # but fallback to sensible values derived from other parts otherwise. - usb_pid = board.get("build.arduino.earlephilhower.usb_pid", + usb_pid = board.get("build.arduino.openwch.usb_pid", board.get("build.hwids", [[0, 0]])[0][1]) - usb_vid = board.get("build.arduino.earlephilhower.usb_vid", + usb_vid = board.get("build.arduino.openwch.usb_vid", board.get("build.hwids", [[0, 0]])[0][0]) usb_manufacturer = board.get( "build.arduino.openwch.usb_manufacturer", board.get("vendor", "WCH")) From f76a26c6cb41297d4f4859741a51b2942ab42d35 Mon Sep 17 00:00:00 2001 From: Koki Mizumoto <21km43@gmail.com> Date: Thu, 12 Sep 2024 11:10:12 +0900 Subject: [PATCH 12/20] Delete USB PD improve (for PR) --- .../usbpd_sink_request_voltage.ino | 5 +---- libraries/USBPD_SINK/src/usbpd_sink.c | 9 ++++----- libraries/USBPD_SINK/src/usbpd_sink.h | 3 +-- 3 files changed, 6 insertions(+), 11 deletions(-) diff --git a/libraries/USBPD_SINK/examples/usbpd_sink_request_voltage/usbpd_sink_request_voltage.ino b/libraries/USBPD_SINK/examples/usbpd_sink_request_voltage/usbpd_sink_request_voltage.ino index d9d82ab2..6193386d 100644 --- a/libraries/USBPD_SINK/examples/usbpd_sink_request_voltage/usbpd_sink_request_voltage.ino +++ b/libraries/USBPD_SINK/examples/usbpd_sink_request_voltage/usbpd_sink_request_voltage.ino @@ -20,10 +20,7 @@ void loop() { if(usbpd_sink_get_ready()) { - if(usbpd_sink_set_request_fixed_voltage(setVoltage) == false) - { - Serial.printf("unsupported voltage\r\n"); - } + usbpd_sink_set_request_fixed_voltage(setVoltage); } // button, myIndex++ diff --git a/libraries/USBPD_SINK/src/usbpd_sink.c b/libraries/USBPD_SINK/src/usbpd_sink.c index 82f166b1..24486ca9 100644 --- a/libraries/USBPD_SINK/src/usbpd_sink.c +++ b/libraries/USBPD_SINK/src/usbpd_sink.c @@ -38,7 +38,7 @@ void usbpd_sink_clear_ready(void) pdControl_g.cc_USBPD_READY = 0; } -bool usbpd_sink_set_request_fixed_voltage(Request_voltage_t requestVoltage) +void usbpd_sink_set_request_fixed_voltage(Request_voltage_t requestVoltage) { uint16_t targetVoltage; switch (requestVoltage) @@ -73,12 +73,11 @@ bool usbpd_sink_set_request_fixed_voltage(Request_voltage_t requestVoltage) if(pdControl_g.cc_FixedSourceCap[i].Voltage == targetVoltage) { pdControl_g.cc_SetPDONum = i+1; - return true; + return; } } - - // unsupported voltage - return false; + pdControl_g.cc_SetPDONum = (pdControl_g.cc_SourcePDONum - pdControl_g.cc_SourcePPSNum); + } void timer3_init(uint16_t arr, uint16_t psc) diff --git a/libraries/USBPD_SINK/src/usbpd_sink.h b/libraries/USBPD_SINK/src/usbpd_sink.h index 12dcc278..1672d048 100644 --- a/libraries/USBPD_SINK/src/usbpd_sink.h +++ b/libraries/USBPD_SINK/src/usbpd_sink.h @@ -5,7 +5,6 @@ extern "C" { #endif /* end of __cplusplus */ -#include #include "usbpd_def.h" // Register Bit Definition @@ -202,7 +201,7 @@ void usbpd_sink_process(void); uint8_t usbpd_sink_get_ready(void); void usbpd_sink_clear_ready(void); -bool usbpd_sink_set_request_fixed_voltage(Request_voltage_t requestVoltage); +void usbpd_sink_set_request_fixed_voltage(Request_voltage_t requestVoltage); #ifdef __cplusplus From a723c2a862fbc14b1050c6199b0ac3b378c23ba1 Mon Sep 17 00:00:00 2001 From: Koki Mizumoto <21km43@gmail.com> Date: Thu, 12 Sep 2024 11:11:57 +0900 Subject: [PATCH 13/20] space --- libraries/USBPD_SINK/src/usbpd_sink.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/USBPD_SINK/src/usbpd_sink.c b/libraries/USBPD_SINK/src/usbpd_sink.c index 24486ca9..0292e38b 100644 --- a/libraries/USBPD_SINK/src/usbpd_sink.c +++ b/libraries/USBPD_SINK/src/usbpd_sink.c @@ -77,7 +77,7 @@ void usbpd_sink_set_request_fixed_voltage(Request_voltage_t requestVoltage) } } pdControl_g.cc_SetPDONum = (pdControl_g.cc_SourcePDONum - pdControl_g.cc_SourcePPSNum); - + } void timer3_init(uint16_t arr, uint16_t psc) From aa33e262f7dc8c8166d6ca490573f41dad8f78cb Mon Sep 17 00:00:00 2001 From: Koki Mizumoto <21km43@gmail.com> Date: Sun, 15 Sep 2024 08:48:16 +0900 Subject: [PATCH 14/20] disable tinyusb for ch32l103 --- boards.txt | 6 ------ system/CH32L10x/SRC/Peripheral/inc/ch32l103.h | 2 +- tools/makeboards.py | 2 +- 3 files changed, 2 insertions(+), 8 deletions(-) diff --git a/boards.txt b/boards.txt index 47179701..32fbe00a 100644 --- a/boards.txt +++ b/boards.txt @@ -797,12 +797,6 @@ CH32L10x_EVT.menu.pnum.CH32L103C8T6.build.IQ_math_RV32= CH32L10x_EVT.menu.pnum.CH32L103C8T6.build.ch_extra_lib=-lprintf -# USB support -CH32L10x_EVT.menu.usb.none=None -CH32L10x_EVT.menu.usb.none.build.usb_flags= -CH32L10x_EVT.menu.usb.tinyusb_usbfs=Adafruit TinyUSB with USBFS -CH32L10x_EVT.menu.usb.tinyusb_usbfs.build.usb_flags=-DUSBCON -DUSE_TINYUSB -DCFG_TUD_WCH_USBIP_USBFS=1 "-I{runtime.platform.path}/libraries/Adafruit_TinyUSB_Arduino/src/arduino" - # Upload menu CH32L10x_EVT.menu.upload_method.swdMethod=WCH-SWD CH32L10x_EVT.menu.upload_method.swdMethod.upload.protocol= diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103.h index e6b98783..e5625523 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103.h @@ -3957,7 +3957,7 @@ typedef struct #define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ #define RCC_PLLMULL18 ((uint32_t)0x003C0000) /* PLL input clock*18 */ -#define RCC_CFGR0_USBPRE ((uint32_t)0x00C00000) /* USBPRE[1:0] bits*/ +#define RCC_CFGR0_USBPRE ((uint32_t)0x00C00000) /* USBPRE[1:0] bits */ #define RCC_USBPRE_0 ((uint32_t)0x00400000) /* Bit 0 */ #define RCC_USBPRE_1 ((uint32_t)0x00800000) /* Bit 1 */ diff --git a/tools/makeboards.py b/tools/makeboards.py index 0ab5e14a..71a526ed 100644 --- a/tools/makeboards.py +++ b/tools/makeboards.py @@ -96,7 +96,7 @@ 'CH32L10x': { 'name': 'CH32L10x_EVT', 'info': '-lprintf', - 'usb': ['tinyusb_usbfs'], + 'usb': [], 'hsi': [96, 72, 56, 48, 0, 'HSI_LP'], 'hse': [96, 72, 56, 48, 0], 'pnums': { From ffd96548c0f1937ca5a656ea12af468d20c5f355 Mon Sep 17 00:00:00 2001 From: Koki Mizumoto <21km43@gmail.com> Date: Thu, 26 Sep 2024 16:35:50 +0900 Subject: [PATCH 15/20] submodule update to 3.3.4 --- libraries/Adafruit_TinyUSB_Arduino | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/Adafruit_TinyUSB_Arduino b/libraries/Adafruit_TinyUSB_Arduino index 05686e7f..a529a74e 160000 --- a/libraries/Adafruit_TinyUSB_Arduino +++ b/libraries/Adafruit_TinyUSB_Arduino @@ -1 +1 @@ -Subproject commit 05686e7f97de299487fc2291864591d0a18d9bb6 +Subproject commit a529a74e4f5018ad95b0524807b5e508871c7831 From ad3a8c4cb52319df431672422d97e758e5cb829b Mon Sep 17 00:00:00 2001 From: 21km43 Date: Mon, 16 Dec 2024 16:47:50 +0900 Subject: [PATCH 16/20] usbpd --- libraries/USBPD_SINK/src/usbpd_sink.c | 35 +++++++++++++++++++++++++++ libraries/USBPD_SINK/src/usbpd_sink.h | 8 ++++++ 2 files changed, 43 insertions(+) diff --git a/libraries/USBPD_SINK/src/usbpd_sink.c b/libraries/USBPD_SINK/src/usbpd_sink.c index 82f166b1..4df22c3c 100644 --- a/libraries/USBPD_SINK/src/usbpd_sink.c +++ b/libraries/USBPD_SINK/src/usbpd_sink.c @@ -38,6 +38,41 @@ void usbpd_sink_clear_ready(void) pdControl_g.cc_USBPD_READY = 0; } +uint8_t usbpd_sink_get_pdo_num(void) +{ + return pdControl_g.cc_SourcePDONum; +} + +uint8_t usbpd_sink_get_pps_num(void) +{ + return pdControl_g.cc_SourcePPSNum; +} + +uint16_t usbpd_sink_get_pdo_voltage(int index) +{ + return pdControl_g.cc_FixedSourceCap[index].Voltage; +} + +uint16_t usbpd_sink_get_pdo_current(int index) +{ + return pdControl_g.cc_FixedSourceCap[index].Current; +} + +uint16_t usbpd_sink_get_pps_min_voltage(int index) +{ + return pdControl_g.cc_PPSSourceCap[index].MinVoltage; +} + +uint16_t usbpd_sink_get_pps_max_voltage(int index) +{ + return pdControl_g.cc_PPSSourceCap[index].MaxVoltage; +} + +uint16_t usbpd_sink_get_pps_current(int index) +{ + return pdControl_g.cc_PPSSourceCap[index].Current; +} + bool usbpd_sink_set_request_fixed_voltage(Request_voltage_t requestVoltage) { uint16_t targetVoltage; diff --git a/libraries/USBPD_SINK/src/usbpd_sink.h b/libraries/USBPD_SINK/src/usbpd_sink.h index 12dcc278..4c03a1e1 100644 --- a/libraries/USBPD_SINK/src/usbpd_sink.h +++ b/libraries/USBPD_SINK/src/usbpd_sink.h @@ -202,6 +202,14 @@ void usbpd_sink_process(void); uint8_t usbpd_sink_get_ready(void); void usbpd_sink_clear_ready(void); +uint8_t usbpd_sink_get_pdo_num(void); +uint8_t usbpd_sink_get_pps_num(void); +uint16_t usbpd_sink_get_pdo_voltage(int index); +uint16_t usbpd_sink_get_pdo_current(int index); +uint16_t usbpd_sink_get_pps_min_voltage(int index); +uint16_t usbpd_sink_get_pps_max_voltage(int index); +uint16_t usbpd_sink_get_pps_current(int index); + bool usbpd_sink_set_request_fixed_voltage(Request_voltage_t requestVoltage); From 1e9073e9bb96b66619b5e165fdee5529224a76b7 Mon Sep 17 00:00:00 2001 From: Koki Mizumoto <21km43@gmail.com> Date: Fri, 10 Jan 2025 23:44:36 +0900 Subject: [PATCH 17/20] ch32l103 sdk update --- system/CH32L10x/SRC/Debug/debug.c | 3 - system/CH32L10x/SRC/Debug/debug.h | 3 +- system/CH32L10x/SRC/Peripheral/inc/ch32l103.h | 42 +++++------ .../SRC/Peripheral/inc/ch32l103_adc.h | 9 +-- .../SRC/Peripheral/inc/ch32l103_exti.h | 3 +- .../SRC/Peripheral/inc/ch32l103_gpio.h | 4 +- .../SRC/Peripheral/inc/ch32l103_i2c.h | 4 +- .../SRC/Peripheral/inc/ch32l103_lptim.h | 28 ++++--- .../SRC/Peripheral/inc/ch32l103_opa.h | 29 +++++++- .../SRC/Peripheral/inc/ch32l103_spi.h | 7 +- .../SRC/Peripheral/src/ch32l103_adc.c | 62 +++------------- .../SRC/Peripheral/src/ch32l103_dbgmcu.c | 4 +- .../SRC/Peripheral/src/ch32l103_flash.c | 4 +- .../SRC/Peripheral/src/ch32l103_gpio.c | 74 +++++++------------ .../SRC/Peripheral/src/ch32l103_iwdg.c | 5 +- .../SRC/Peripheral/src/ch32l103_lptim.c | 11 ++- .../SRC/Peripheral/src/ch32l103_opa.c | 32 ++++++-- .../SRC/Peripheral/src/ch32l103_rcc.c | 2 +- .../SRC/Peripheral/src/ch32l103_spi.c | 5 +- .../CH32L10x/SRC/Startup/startup_ch32l103.S | 6 +- system/CH32L10x/USER/ch32l103_it.c | 3 +- 21 files changed, 155 insertions(+), 185 deletions(-) diff --git a/system/CH32L10x/SRC/Debug/debug.c b/system/CH32L10x/SRC/Debug/debug.c index efcee4cd..76433342 100644 --- a/system/CH32L10x/SRC/Debug/debug.c +++ b/system/CH32L10x/SRC/Debug/debug.c @@ -149,8 +149,6 @@ void USART_Printf_Init(uint32_t baudrate) * * @return size: Data length */ - -#if 0 __attribute__((used)) int _write(int fd, char *buf, int size) { @@ -171,7 +169,6 @@ int _write(int fd, char *buf, int size) return size; } -#endif /********************************************************************* * @fn _sbrk diff --git a/system/CH32L10x/SRC/Debug/debug.h b/system/CH32L10x/SRC/Debug/debug.h index 9c2379e1..db1175d5 100644 --- a/system/CH32L10x/SRC/Debug/debug.h +++ b/system/CH32L10x/SRC/Debug/debug.h @@ -2,7 +2,7 @@ * File Name : debug.h * Author : WCH * Version : V1.0.0 - * Date : 2023/07/08 + * Date : 2023/11/06 * Description : This file contains all the functions prototypes for UART * Printf , Delay functions. ********************************************************************************* @@ -34,6 +34,7 @@ extern uint32_t OPA_Trim; extern uint16_t ADC_Trim; extern uint32_t TS_Val; extern uint32_t CHIPID; +extern uint16_t USBPD_CFG; void Delay_Init(void); void Delay_Us(uint32_t n); diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103.h index e5625523..3b49e36e 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103.h @@ -2,7 +2,7 @@ * File Name : ch32l103.h * Author : WCH * Version : V1.0.0 - * Date : 2023/07/08 + * Date : 2024/11/06 * Description : CH32L103 Device Peripheral Access Layer Header File. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -16,7 +16,9 @@ extern "C" { #endif +#ifndef HSE_VALUE #define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */ +#endif /* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ #define HSE_STARTUP_TIMEOUT ((uint16_t)0x1000) /* Time out for HSE start up */ @@ -27,7 +29,7 @@ extern "C" { /* Standard Peripheral Library version number */ #define __CH32L103_STDPERIPH_VERSION_MAIN (0x01) /* [15:8] main version */ -#define __CH32L103_STDPERIPH_VERSION_SUB (0x00) /* [7:0] sub version */ +#define __CH32L103_STDPERIPH_VERSION_SUB (0x03) /* [7:0] sub version */ #define __CH32L103_STDPERIPH_VERSION ((__CH32L103_STDPERIPH_VERSION_MAIN << 8)\ |(__CH32L103_STDPERIPH_VERSION_SUB << 0)) @@ -40,7 +42,7 @@ typedef enum IRQn Ecall_M_Mode_IRQn = 5, /* Ecall M Mode Interrupt */ Ecall_U_Mode_IRQn = 8, /* Ecall U Mode Interrupt */ Break_Point_IRQn = 9, /* Break Point Interrupt */ - SysTicK_IRQn = 12, /* System timer Interrupt */ + SysTick_IRQn = 12, /* System timer Interrupt */ Software_IRQn = 14, /* Software Interrupt */ /****** RISC-V specific Interrupt Numbers *********************************************************/ @@ -94,7 +96,7 @@ typedef enum IRQn LPTIM_IRQn = 63, /* LPTIM global Interrupt */ OPA_IRQn = 64, /* OPA global Interrupt */ USBPD_IRQn = 65, /* USBPD global Interrupt */ - TKeyWakeUp_IRQn = 66, /* TKey WakeUp Interrupt */ + USBPDWakeUp_IRQn = 67, /* USBPD WakeUp Interrupt */ CMPWakeUp_IRQn = 68, /* CMP WakeUp Interrupt */ @@ -102,6 +104,7 @@ typedef enum IRQn #define HardFault_IRQn EXC_IRQn #define ADC1_2_IRQn ADC_IRQn +#define SysTicK_IRQn SysTick_IRQn #include #include "core_riscv.h" @@ -166,13 +169,7 @@ typedef struct __IO uint16_t TPCTLR; uint16_t RESERVED12; __IO uint16_t TPCSR; - uint16_t RESERVED13[5]; - __IO uint16_t DATAR11; - uint16_t RESERVED14; - __IO uint16_t DATAR12; - uint16_t RESERVED15; - __IO uint16_t DATAR13; - uint16_t RESERVED16; + uint16_t RESERVED13; } BKP_TypeDef; /* Controller Area Network TxMailBox */ @@ -824,7 +821,7 @@ typedef struct #define ADC_TRIM_BASE ((uint32_t)0x1FFFF728) #define HSI_LP_TRIM_BASE ((uint32_t)0x1FFFF72A) #define CHIPID_BASE ((uint32_t)0x1FFFF704) - +#define USBPD_CFG_BASE ((uint32_t)0x1FFFF730) /* Peripheral declaration */ #define TIM2 ((TIM_TypeDef *)TIM2_BASE) @@ -906,8 +903,9 @@ typedef struct #define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ #define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ #define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ -#define ADC_RDISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ #define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ +#define ADC_RDISCEN ADC_DISCEN #define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ #define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ @@ -1278,15 +1276,6 @@ typedef struct /******************* Bit definition for BKP_DATAR10 register *******************/ #define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */ -/******************* Bit definition for BKP_DATAR11 register *******************/ -#define BKP_DATAR11_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR12 register *******************/ -#define BKP_DATAR12_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR13 register *******************/ -#define BKP_DATAR13_D ((uint16_t)0xFFFF) /* Backup data */ - /****************** Bit definition for BKP_OCTLR register *******************/ #define BKP_CAL ((uint16_t)0x007F) /* Calibration value */ #define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */ @@ -3547,7 +3536,8 @@ typedef struct #define AFIO_PCFR1_CAN_RM_0 ((uint32_t)0x00002000) /* Bit 0 */ #define AFIO_PCFR1_CAN_RM_1 ((uint32_t)0x00004000) /* Bit 1 */ -#define AFIO_PCFR1_PD01_RM ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCFR1_PD0PD1_RM ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCFR1_PD01_RM AFIO_PCFR1_PD0PD1_RM #define AFIO_PCFR1_SW_CFG ((uint32_t)0x07000000) /* SW_CFG[2:0] bits (SDI configuration) */ #define AFIO_PCFR1_SW_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ @@ -3957,7 +3947,7 @@ typedef struct #define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ #define RCC_PLLMULL18 ((uint32_t)0x003C0000) /* PLL input clock*18 */ -#define RCC_CFGR0_USBPRE ((uint32_t)0x00C00000) /* USBPRE[1:0] bits */ +#define RCC_CFGR0_USBPRE ((uint32_t)0x00C00000) /* USBPRE[1:0] bits*/ #define RCC_USBPRE_0 ((uint32_t)0x00400000) /* Bit 0 */ #define RCC_USBPRE_1 ((uint32_t)0x00800000) /* Bit 1 */ @@ -4643,6 +4633,7 @@ typedef struct /******************* Bit definition for OPA_CFGR2 register *******************/ #define OPA_CFGR2_POLL_VLU ((uint32_t)0x000001FF) #define OPA_CFGR2_POLL_NUM ((uint32_t)0x00000E00) +#define OPA_CFGR2_POLL_CNT ((uint32_t)0x00007000) /******************* Bit definition for OPA_CTLR1 register *******************/ #define OPA_CTLR1_EN1 ((uint32_t)0x00000001) @@ -4661,16 +4652,19 @@ typedef struct #define OPA_CTLR2_MODE1 ((uint32_t)0x00000006) #define OPA_CTLR2_NSEL1 ((uint32_t)0x00000008) #define OPA_CTLR2_PSEL1 ((uint32_t)0x00000010) +#define OPA_CTLR2_HYEN1 ((uint32_t)0x00000020) #define OPA_CTLR2_LP1 ((uint32_t)0x00000040) #define OPA_CTLR2_EN2 ((uint32_t)0x00000100) #define OPA_CTLR2_MODE2 ((uint32_t)0x00000600) #define OPA_CTLR2_NSEL2 ((uint32_t)0x00000800) #define OPA_CTLR2_PSEL2 ((uint32_t)0x00001000) +#define OPA_CTLR2_HYEN2 ((uint32_t)0x00002000) #define OPA_CTLR2_LP2 ((uint32_t)0x00004000) #define OPA_CTLR2_EN3 ((uint32_t)0x00010000) #define OPA_CTLR2_MODE3 ((uint32_t)0x00060000) #define OPA_CTLR2_NSEL3 ((uint32_t)0x00080000) #define OPA_CTLR2_PSEL3 ((uint32_t)0x00100000) +#define OPA_CTLR2_HYEN3 ((uint32_t)0x00200000) #define OPA_CTLR2_LP3 ((uint32_t)0x00400000) #define OPA_CTLR2_WKUP_MD ((uint32_t)0x03000000) diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_adc.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_adc.h index f411e1e2..7494a2c1 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_adc.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_adc.h @@ -2,7 +2,7 @@ * File Name : ch32l103_adc.h * Author : WCH * Version : V1.0.0 - * Date : 2023/07/08 + * Date : 2024/05/06 * Description : This file contains all the functions prototypes for the * ADC firmware library. ********************************************************************************* @@ -153,12 +153,6 @@ typedef struct #define ADC_FLAG_JSTRT ((uint8_t)0x08) #define ADC_FLAG_STRT ((uint8_t)0x10) -/* ADC_TKey_WakeUp_IO_mode_definition */ -#define ADC_TKey_WakeUp_Mode0 ((uint32_t)0x00000000) -#define ADC_TKey_WakeUp_Mode1 ((uint32_t)0x00080000) -#define ADC_TKey_WakeUp_Mode2 ((uint32_t)0x00100000) -#define ADC_TKey_WakeUp_Mode3 ((uint32_t)0x00180000) - /* ADC_Sample_mode_definition */ #define ADC_Sample_NoOver_1M_Mode ((uint32_t)0x00000000) #define ADC_Sample_Over_1M_Mode ((uint32_t)0x00000020) @@ -202,7 +196,6 @@ ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); s32 TempSensor_Volt_To_Temper(s32 Value); void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_TKey_WakeUpCmd(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint32_t IO_Mode, FunctionalState NewState); void ADC_TKey_ChannelxMulShieldCmd(ADC_TypeDef *ADCx, uint8_t ADC_Channel, FunctionalState NewState); void ADC_TKey_MulShieldCmd(ADC_TypeDef *ADCx, FunctionalState NewState); void ADC_DutyDelayCmd(ADC_TypeDef *ADCx, FunctionalState NewState); diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_exti.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_exti.h index 72841bcb..058a1957 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_exti.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_exti.h @@ -2,7 +2,7 @@ * File Name : ch32l103_exti.h * Author : WCH * Version : V1.0.0 - * Date : 2023/07/08 + * Date : 2024/05/06 * Description : This file contains all the functions prototypes for the * EXTI firmware library. ********************************************************************************* @@ -69,7 +69,6 @@ typedef struct #define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ #define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */ #define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */ -#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the Tkey Wakeup event */ #define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the USBPD Wakeup event */ #define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBFS Wakeup event */ #define EXTI_Line21 ((uint32_t)0x200000) /* External interrupt line 21 Connected to the LPTIM Wakeup event */ diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_gpio.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_gpio.h index f41baa21..810bf66a 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_gpio.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_gpio.h @@ -2,7 +2,7 @@ * File Name : ch32l103_gpio.h * Author : WCH * Version : V1.0.0 - * Date : 2023/07/08 + * Date : 2024/03/01 * Description : This file contains all the functions prototypes for the * GPIO firmware library. ********************************************************************************* @@ -121,7 +121,7 @@ typedef enum #define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ #define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ #define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */ -#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* GPIO_Remap_SWJ_Disable - Full SDI Disabled (SDI) */ //bit[31:30] = 01b - PCFR2 #define GPIO_Remap_USART4 ((uint32_t)0x40000001) /* USART4 Alternate Function mapping */ diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_i2c.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_i2c.h index 1cb04245..6489e8e3 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_i2c.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_i2c.h @@ -106,7 +106,7 @@ typedef struct #define I2C_IT_ADDR ((uint32_t)0x02000002) #define I2C_IT_SB ((uint32_t)0x02000001) -/* SR2 register flags */ +/* STAR2 register flags */ #define I2C_FLAG_DUALF ((uint32_t)0x00800000) #define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) @@ -115,7 +115,7 @@ typedef struct #define I2C_FLAG_BUSY ((uint32_t)0x00020000) #define I2C_FLAG_MSL ((uint32_t)0x00010000) -/* SR1 register flags */ +/* STAR1 register flags */ #define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) #define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) #define I2C_FLAG_PECERR ((uint32_t)0x10001000) diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_lptim.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_lptim.h index 00f7517f..5f4a1adf 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_lptim.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_lptim.h @@ -2,7 +2,7 @@ * File Name : ch32l103_lptim.h * Author : WCH * Version : V1.0.0 - * Date : 2023/07/08 + * Date : 2024/07/15 * Description : This file contains all the functions prototypes for the * TIM firmware library. ********************************************************************************* @@ -53,11 +53,11 @@ typedef struct FunctionalState LPTIM_OnePulseMode; /* Specifies whether the PWM out one pulse. This parameter can be set to ENABLE or DISABLE */ - uint32_t LPYIM_OutputPolarity; /* Configures output polarity. - This parameter can be a value of @ref LPYIM_OutputPolarity */ + uint32_t LPTIM_OutputPolarity; /* Configures output polarity. + This parameter can be a value of @ref LPTIM_OutputPolarity */ - uint32_t LPYIM_UpdateMode; /* Configures update mode. - This parameter can be a value of @ref LPYIM_UpdateMode */ + uint32_t LPTIM_UpdateMode; /* Configures update mode. + This parameter can be a value of @ref LPTIM_UpdateMode */ uint32_t LPTIM_CountSource; /* Configures Counter Source. This parameter can be a value of @ref LPTIM_CountSource */ @@ -133,13 +133,13 @@ typedef struct #define LPTIM_ExTriggerPolarity_Falling ((uint32_t)0x00040000) #define LPTIM_ExTriggerPolarity_Rising_Falling ((uint32_t)0x00060000) -/* LPYIM_OutputPolarity */ -#define LPYIM_OutputPolarity_High ((uint32_t)0x00000000) -#define LPYIM_OutputPolarity_Low ((uint32_t)0x00200000) +/* LPTIM_OutputPolarity */ +#define LPTIM_OutputPolarity_High ((uint32_t)0x00000000) +#define LPTIM_OutputPolarity_Low ((uint32_t)0x00200000) -/* LPYIM_UpdateMode */ -#define LPYIM_UpdateMode0 ((uint32_t)0x00000000) -#define LPYIM_UpdateMode1 ((uint32_t)0x00400000) +/* LPTIM_UpdateMode */ +#define LPTIM_UpdateMode0 ((uint32_t)0x00000000) +#define LPTIM_UpdateMode1 ((uint32_t)0x00400000) /* LPTIM_CountSource */ #define LPTIM_CountSource_Internal ((uint32_t)0x00000000) @@ -171,6 +171,12 @@ typedef struct #define LPTIM_IT_CMPM ((uint32_t)0x00000001) +#define LPYIM_OutputPolarity_High LPTIM_OutputPolarity_High +#define LPYIM_OutputPolarity_Low LPTIM_OutputPolarity_Low +#define LPYIM_UpdateMode0 LPTIM_UpdateMode0 +#define LPYIM_UpdateMode1 LPTIM_UpdateMode1 + + void LPTIM_DeInit(void); void LPTIM_TimeBaseInit(LPTIM_TimeBaseInitTypeDef* LPTIM_TimeBaseInitStruct); void LPTIM_TimeBaseStructInit(LPTIM_TimeBaseInitTypeDef* LPTIM_TimeBaseInitStruct); diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_opa.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_opa.h index daf0222c..93a59016 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_opa.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_opa.h @@ -2,7 +2,7 @@ * File Name : ch32l103_opa.h * Author : WCH * Version : V1.0.0 - * Date : 2023/07/08 + * Date : 2024/11/05 * Description : This file contains all the functions prototypes for the * OPA firmware library. ********************************************************************************* @@ -177,10 +177,20 @@ typedef enum /* CMP_PSEL_enumeration */ typedef enum { - CMP_CHP1 = 0, - CMP_CHP2, + CMP_CHP_0 = 0, + CMP_CHP_1, } CMP_PSEL_TypeDef; +#define CMP_CHP1 CMP_CHP_0 +#define CMP_CHP2 CMP_CHP_1 + +/* CMP_HYEN_enumeration */ +typedef enum +{ + CMP_HYEN0 = 0, + CMP_HYEN1, +} CMP_HYEN_TypeDef; + /* CMP Init Structure definition */ typedef struct { @@ -188,8 +198,20 @@ typedef struct CMP_Mode_TypeDef Mode; /* Specifies the mode of CMP */ CMP_NSEL_TypeDef NSEL; /* Specifies the negative channel of CMP */ CMP_PSEL_TypeDef PSEL; /* Specifies the positive channel of CMP */ + CMP_HYEN_TypeDef HYEN; /* Specifies the hysteresis comparator of CMP */ } CMP_InitTypeDef; +/* Current channel for OPA polling enumeration */ +typedef enum +{ + O1P0 = 0, + O1P1, + O1P2, + O1P3, + O1P4, + O1P5, +} OPA_POLL_NUM_TypeDef; + /* OPA_flags_definition */ #define OPA_FLAG_OUT_OPA1 ((uint16_t)0x1000) #define OPA_FLAG_OUT_CNT ((uint16_t)0x4000) @@ -212,6 +234,7 @@ void OPA_CMP_LP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState); void OPA_CMP_WakeUp_ModeConfig(uint32_t CMP_WakeUP_Mode); FlagStatus OPA_GetFlagStatus( uint16_t OPA_FLAG); void OPA_ClearFlag(uint16_t OPA_FLAG); +OPA_POLL_NUM_TypeDef OPA_POLL_CNT(void); #ifdef __cplusplus } diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_spi.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_spi.h index 888734ff..d1189a92 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_spi.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_spi.h @@ -2,7 +2,7 @@ * File Name : ch32l103_spi.h * Author : WCH * Version : V1.0.0 - * Date : 2023/07/08 + * Date : 2024/06/05 * Description : This file contains all the functions prototypes for the * SPI firmware library. ********************************************************************************* @@ -32,7 +32,8 @@ typedef struct This parameter can be a value of @ref SPI_data_size */ uint16_t SPI_CPOL; /* Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ + This parameter can be a value of @ref SPI_Clock_Polarity + When using SPI slave mode to send data, the CPOL bit should be set to 1 */ uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_Clock_Phase */ @@ -69,7 +70,7 @@ typedef struct /* SPI_Clock_Polarity */ #define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) +#define SPI_CPOL_High ((uint16_t)0x0002)//When using SPI slave mode to send data, the CPOL bit should be set to 1. /* SPI_Clock_Phase */ #define SPI_CPHA_1Edge ((uint16_t)0x0000) diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_adc.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_adc.c index ce3919a7..da3b4f74 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_adc.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_adc.c @@ -2,7 +2,7 @@ * File Name : ch32l103_adc.c * Author : WCH * Version : V1.0.0 - * Date : 2024/01/19 + * Date : 2024/05/06 * Description : This file provides all the ADC firmware functions. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -1122,48 +1122,6 @@ void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState) } } -/********************************************************************* - * @fn ADC_TKey_WakeUpCmd - * - * @brief Enables or disables TKey wake up of the selected ADC channel - * and Configures IO mode. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_8 - ADC Channel8 selected. - * ADC_Channel_9 - ADC Channel9 selected. - * IO_Mode - IO state before wake up - * ADC_TKey_WakeUp_Mode0 - * ADC_TKey_WakeUp_Mode1 - * ADC_TKey_WakeUp_Mode2 - * ADC_TKey_WakeUp_Mode3 - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_TKey_WakeUpCmd(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint32_t IO_Mode, FunctionalState NewState) -{ - ADCx->CFG &= ~ADC_TKey_WakeUp_Mode3; - ADCx->CFG |= IO_Mode; - - if(NewState != DISABLE) - { - ADCx->CFG |= ((1<<21) << ADC_Channel); - } - else - { - ADCx->CFG &= ~((1<<21) << ADC_Channel); - } -} - /********************************************************************* * @fn ADC_TKey_ChannelxMulShieldCmd * @@ -1253,6 +1211,16 @@ void ADC_DutyDelayCmd(ADC_TypeDef *ADCx, FunctionalState NewState) */ void ADC_FIFO_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) { + FLASH->KEYR = CFG_KEY1; + FLASH->KEYR = CFG_KEY2; + FLASH->MODEKEYR = CFG_KEY1; + FLASH->OBKEYR = CFG_KEY2; + while((*(vu32*)0x40022034) & (1<<29)); // wait unlock + + *(vu32*)0x4002202C |= (1<<9); //offset calibration + (*(vu32*)0x40022034) |= (1<<29); //lock + while((*(vu32*)0x40022034) & (1<<29) == 0); //wait lock + if(NewState != DISABLE) { ADCx->CFG |= (1 << 6); @@ -1335,15 +1303,7 @@ int16_t Get_CalibrationValue(ADC_TypeDef *ADCx) __IO uint8_t i, j; uint16_t buf[10]; __IO uint16_t t; - FLASH->KEYR = CFG_KEY1; - FLASH->KEYR = CFG_KEY2; - FLASH->MODEKEYR = CFG_KEY1; - FLASH->OBKEYR = CFG_KEY2; - while((*(vu32*)0x40022034) & (1<<29)); // wait unlock - *(vu32*)0x4002202C |= (1<<9); - (*(vu32*)0x40022034) |= (1<<29); //lock - while((*(vu32*)0x40022034) & (1<<29) == 0); //wait lock ADC1->CTLR2|=(7<<17); ADC_Cmd(ADC1, ENABLE); ADC_FIFO_Cmd(ADC1, ENABLE); diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_dbgmcu.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_dbgmcu.c index 9004d684..44ec56c5 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_dbgmcu.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_dbgmcu.c @@ -2,7 +2,7 @@ * File Name : ch32l103_dbgmcu.c * Author : WCH * Version : V1.0.0 - * Date : 2023/07/08 + * Date : 2024/05/06 * Description : This file provides all the DBGMCU firmware functions. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -113,13 +113,11 @@ void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) * * @return Device identifier. * ChipID List- - * CH32L103C8U6-0x103007x0 * CH32L103C8T6-0x103107x0 * CH32L103F8P6-0x103A07x0 * CH32L103G8R6-0x103B07x0 * CH32L103K8U6-0x103207x0 * CH32L103F8U6-0x103D07x0 - * CH32L103F7P6-0x103707x0 * */ uint32_t DBGMCU_GetCHIPID( void ) diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_flash.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_flash.c index e9495ec2..e602af08 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_flash.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_flash.c @@ -2,7 +2,7 @@ * File Name : ch32l103_flash.c * Author : WCH * Version : V1.0.0 - * Date : 2023/07/08 + * Date : 2024/04/26 * Description : This file provides all the FLASH firmware functions. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -56,7 +56,7 @@ /* Flash Program Valid Address */ #define ValidAddrStart (FLASH_BASE) -#define ValidAddrEnd (FLASH_BASE + 0xF800) +#define ValidAddrEnd (FLASH_BASE + 0x10000) /* FLASH Size */ #define Size_256B 0x100 diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_gpio.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_gpio.c index 8769f7d7..57458336 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_gpio.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_gpio.c @@ -2,7 +2,7 @@ * File Name : ch32l103_gpio.c * Author : WCH * Version : V1.0.0 - * Date : 2023/07/08 + * Date : 2024/11/06 * Description : This file provides all the GPIO firmware functions. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -26,7 +26,7 @@ uint32_t OPA_Trim = 0; uint16_t ADC_Trim = 0; uint32_t TS_Val = 0; uint32_t CHIPID = 0; - +uint16_t USBPD_CFG = 0; /********************************************************************* * @fn GPIO_DeInit * @@ -597,6 +597,7 @@ void GPIO_IPD_Unused(void) ADC_Trim = (*(uint16_t *)ADC_TRIM_BASE); TS_Val = (*(uint32_t *)TS_BASE); CHIPID = (*(uint32_t *)CHIPID_BASE); + USBPD_CFG = (*(uint16_t *)USBPD_CFG_BASE); RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOA | RCC_PB2Periph_GPIOB | RCC_PB2Periph_GPIOC |RCC_PB2Periph_GPIOD |RCC_PB2Periph_AFIO,ENABLE); chip = *( uint32_t * )CHIPID_BASE & (~0x000000F0); @@ -604,32 +605,30 @@ void GPIO_IPD_Unused(void) { case 0x10320700: //CH32L103K8U6 { - GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9|GPIO_Pin_10\ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10\ |GPIO_Pin_11|GPIO_Pin_12\ - |GPIO_Pin_13|GPIO_Pin_14\ - |GPIO_Pin_15; + |GPIO_Pin_13|GPIO_Pin_14; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; GPIO_Init(GPIOB, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; GPIO_Init(GPIOC, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOD, &GPIO_InitStructure); break; } case 0x103D0700: //CH32L103F8U6 { - GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE); + GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3\ |GPIO_Pin_4|GPIO_Pin_5\ |GPIO_Pin_8|GPIO_Pin_9\ |GPIO_Pin_12; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; GPIO_Init(GPIOB, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13|GPIO_Pin_14\ |GPIO_Pin_15; @@ -640,73 +639,54 @@ void GPIO_IPD_Unused(void) GPIO_Init(GPIOD, &GPIO_InitStructure); break; } - case 0x10370700: //CH32L103F7P6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\ - |GPIO_Pin_10|GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2\ - |GPIO_Pin_3|GPIO_Pin_4\ - |GPIO_Pin_5|GPIO_Pin_9\ - |GPIO_Pin_10|GPIO_Pin_11\ - |GPIO_Pin_12|GPIO_Pin_13|GPIO_Pin_14\ - |GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13|GPIO_Pin_14\ - |GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOC, &GPIO_InitStructure); - break; - } case 0x103B0700: //CH32L103G8R6 { + GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_9; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4|GPIO_Pin_9; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; GPIO_Init(GPIOB, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13|GPIO_Pin_14\ |GPIO_Pin_15; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; GPIO_Init(GPIOC, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; GPIO_Init(GPIOD, &GPIO_InitStructure); break; } case 0x103A0700: //CH32L103F8P6 { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_15; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2\ - |GPIO_Pin_3|GPIO_Pin_4\ - |GPIO_Pin_5|GPIO_Pin_6\ - |GPIO_Pin_7 |GPIO_Pin_8\ - |GPIO_Pin_9|GPIO_Pin_10\ - |GPIO_Pin_11|GPIO_Pin_12; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13|GPIO_Pin_14\ |GPIO_Pin_15; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; GPIO_Init(GPIOC, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOD, &GPIO_InitStructure); break; } case 0x10310700: //CH32L103C8T6 { break; } - case 0x10300700: //CH32L103C8U6 - { - break; - } default: { break; diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_iwdg.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_iwdg.c index 83e43536..4779397b 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_iwdg.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_iwdg.c @@ -2,7 +2,7 @@ * File Name : ch32l103_iwdg.c * Author : WCH * Version : V1.0.0 - * Date : 2023/12/26 + * Date : 2024/03/26 * Description : This file provides all the IWDG firmware functions. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -92,8 +92,7 @@ void IWDG_ReloadCounter(void) void IWDG_Enable(void) { IWDG->CTLR = CTLR_KEY_Enable; - while(RCC->RSTSCKR | 0x02 != SET) - ; + while((RCC->RSTSCKR & 0x2) == RESET); } /********************************************************************* diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_lptim.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_lptim.c index ac7ae7e0..27597a7a 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_lptim.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_lptim.c @@ -2,7 +2,7 @@ * File Name : ch32l103_lptim.c * Author : WCH * Version : V1.0.0 - * Date : 2023/07/08 + * Date : 2024/08/29 * Description : This file provides all the TIM firmware functions. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -58,9 +58,8 @@ void LPTIM_TimeBaseInit(LPTIM_TimeBaseInitTypeDef *LPTIM_TimeBaseInitStruct) temp1 |= LPTIM_TimeBaseInitStruct->LPTIM_ClockSource | LPTIM_TimeBaseInitStruct->LPTIM_ClockSampleTime \ | LPTIM_TimeBaseInitStruct->LPTIM_TriggerSampleTime | LPTIM_TimeBaseInitStruct->LPTIM_ClockPrescaler \ | LPTIM_TimeBaseInitStruct->LPTIM_TriggerSource | LPTIM_TimeBaseInitStruct->LPTIM_ExTriggerPolarity \ - | LPTIM_TimeBaseInitStruct->LPYIM_OutputPolarity | LPTIM_TimeBaseInitStruct->LPYIM_UpdateMode \ - | LPTIM_TimeBaseInitStruct->LPYIM_UpdateMode | LPTIM_TimeBaseInitStruct->LPTIM_CountSource \ - | LPTIM_TimeBaseInitStruct->LPTIM_InClockSource | LPTIM_TimeBaseInitStruct->LPTIM_CountSource \ + | LPTIM_TimeBaseInitStruct->LPTIM_OutputPolarity | LPTIM_TimeBaseInitStruct->LPTIM_UpdateMode \ + | LPTIM_TimeBaseInitStruct->LPTIM_CountSource | LPTIM_TimeBaseInitStruct->LPTIM_InClockSource \ | (LPTIM_TimeBaseInitStruct->LPTIM_TimeOut << 19) | (LPTIM_TimeBaseInitStruct->LPTIM_OnePulseMode << 20) \ | (LPTIM_TimeBaseInitStruct->LPTIM_Encoder << 24) | (LPTIM_TimeBaseInitStruct->LPTIM_ForceOutHigh << 27); @@ -93,8 +92,8 @@ void LPTIM_TimeBaseStructInit(LPTIM_TimeBaseInitTypeDef *LPTIM_TimeBaseInitStruc LPTIM_TimeBaseInitStruct->LPTIM_ExTriggerPolarity = LPTIM_ExTriggerPolarity_Disable; LPTIM_TimeBaseInitStruct->LPTIM_TimeOut = DISABLE; LPTIM_TimeBaseInitStruct->LPTIM_OnePulseMode = DISABLE; - LPTIM_TimeBaseInitStruct->LPYIM_OutputPolarity = LPYIM_OutputPolarity_High; - LPTIM_TimeBaseInitStruct->LPYIM_UpdateMode = LPYIM_UpdateMode0; + LPTIM_TimeBaseInitStruct->LPTIM_OutputPolarity = LPTIM_OutputPolarity_High; + LPTIM_TimeBaseInitStruct->LPTIM_UpdateMode = LPTIM_UpdateMode0; LPTIM_TimeBaseInitStruct->LPTIM_CountSource = LPTIM_CountSource_Internal; LPTIM_TimeBaseInitStruct->LPTIM_Encoder = DISABLE; LPTIM_TimeBaseInitStruct->LPTIM_InClockSource = LPTIM_InClockSource_PCLK1; diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_opa.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_opa.c index 0c767bab..ed39c5b0 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_opa.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_opa.c @@ -2,7 +2,7 @@ * File Name : ch32l103_opa.c * Author : WCH * Version : V1.0.0 - * Date : 2023/07/08 + * Date : 2024/11/05 * Description : This file provides all the OPA firmware functions. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -15,8 +15,12 @@ #define OPCM_KEY1 ((uint32_t)0x45670123) #define OPCM_KEY2 ((uint32_t)0xCDEF89AB) +/* mask definition*/ +#define POLL_CNT_MASK ((uint16_t)0x7000) + volatile uint32_t CTLR2_tmp = 0; + /******************************************************************************** * @fn OPCM_Unlock * @@ -172,19 +176,19 @@ void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct) { tmp1 &= 0xFFFFFFC1; tmp1 |= (CMP_InitStruct->Mode << 1) | (CMP_InitStruct->NSEL << 3) - | (CMP_InitStruct->PSEL << 4); + | (CMP_InitStruct->PSEL << 4) | (CMP_InitStruct->HYEN <<5); } else if(CMP_InitStruct->CMP_NUM == CMP2) { tmp1 &= 0xFFFFC1FF; tmp1 |= (CMP_InitStruct->Mode << 9) | (CMP_InitStruct->NSEL << 11) - | (CMP_InitStruct->PSEL << 12); + | (CMP_InitStruct->PSEL << 12) | (CMP_InitStruct->HYEN <<13); } else if(CMP_InitStruct->CMP_NUM == CMP3) { tmp1 &= 0xFFC1FFFF; tmp1 |= (CMP_InitStruct->Mode << 17) | (CMP_InitStruct->NSEL << 19) - | (CMP_InitStruct->PSEL << 20); + | (CMP_InitStruct->PSEL << 20) | (CMP_InitStruct->HYEN <<21); } CTLR2_tmp = tmp1; @@ -205,7 +209,7 @@ void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct) CMP_InitStruct->CMP_NUM = CMP1; CMP_InitStruct->Mode = OUT_IO0; CMP_InitStruct->NSEL = CMP_CHN0; - CMP_InitStruct->PSEL = CMP_CHP1; + CMP_InitStruct->PSEL = CMP_CHP_0; } /********************************************************************* @@ -320,4 +324,20 @@ void OPA_ClearFlag(uint16_t OPA_FLAG) OPA->CFGR1 &= (uint16_t)~OPA_FLAG; } - +/********************************************************************* + * @fn OPA_POLL_CNT + * + * @brief Displays the current channel being polled by the OPA + * + * @param none + * + * @return OPA_POLL_NUM_TypeDef - Current channel for OPA polling + */ +OPA_POLL_NUM_TypeDef OPA_POLL_CNT(void) +{ + uint16_t tmp1 = 0; + tmp1 = OPA->CFGR2; + tmp1 &= POLL_CNT_MASK; + tmp1 = tmp1 >> 12; + return tmp1; +} diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_rcc.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_rcc.c index 53287fb3..b701f1dd 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_rcc.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_rcc.c @@ -1002,7 +1002,7 @@ void RCC_ADCCLKDutyCycleConfig(uint32_t RCC_DutyCycle) * @fn RCC_HSE_LP_Cmd * * @brief Enables or disables low power mode of the External High Speed - * oscillator (HSI). + * oscillator (HSE). * * @param NewState - ENABLE or DISABLE. * diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_spi.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_spi.c index 3ce5f960..9197c024 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_spi.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_spi.c @@ -2,7 +2,7 @@ * File Name : ch32l103_spi.c * Author : WCH * Version : V1.0.0 - * Date : 2023/07/08 + * Date : 2024/06/05 * Description : This file provides all the SPI firmware functions. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -59,7 +59,8 @@ void SPI_I2S_DeInit(SPI_TypeDef *SPIx) * @fn SPI_Init * * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. + * parameters in the SPI_InitStruct. + * When using SPI slave mode to send data, the CPOL bit should be set to 1. * * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that diff --git a/system/CH32L10x/SRC/Startup/startup_ch32l103.S b/system/CH32L10x/SRC/Startup/startup_ch32l103.S index eef1c5b8..fbe5f97e 100644 --- a/system/CH32L10x/SRC/Startup/startup_ch32l103.S +++ b/system/CH32L10x/SRC/Startup/startup_ch32l103.S @@ -2,7 +2,7 @@ ;* File Name : startup_ch32l103.s ;* Author : WCH ;* Version : V1.0.0 -;* Date : 2023/11/11 +;* Date : 2024/05/06 ;* Description : CH32L103 vector table for eclipse toolchain. ;********************************************************************************* ;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -87,7 +87,7 @@ _vector_base: .word LPTIM_IRQHandler /* LPTIM */ .word OPA_IRQHandler /* OPA */ .word USBPD_IRQHandler /* USBPD */ - .word TKeyWakeUp_IRQHandler /* TKey Wake Up */ + .word 0 .word USBPDWakeUp_IRQHandler /* USBPD Wake Up */ .word CMPWakeUp_IRQHandler /* CMP Wake Up */ @@ -150,7 +150,6 @@ _vector_base: .weak LPTIM_IRQHandler /* LPTIM */ .weak OPA_IRQHandler /* OPA */ .weak USBPD_IRQHandler /* USBPD */ - .weak TKeyWakeUp_IRQHandler /* TKey Wake Up */ .weak USBPDWakeUp_IRQHandler /* USBPD Wake Up */ .weak CMPWakeUp_IRQHandler /* CMP Wake Up */ @@ -211,7 +210,6 @@ DMA1_Channel8_IRQHandler: LPTIM_IRQHandler: OPA_IRQHandler: USBPD_IRQHandler: -TKeyWakeUp_IRQHandler: USBPDWakeUp_IRQHandler: CMPWakeUp_IRQHandler: 1: diff --git a/system/CH32L10x/USER/ch32l103_it.c b/system/CH32L10x/USER/ch32l103_it.c index b4040b8b..7a8f1322 100644 --- a/system/CH32L10x/USER/ch32l103_it.c +++ b/system/CH32L10x/USER/ch32l103_it.c @@ -2,7 +2,7 @@ * File Name : ch32l103_it.c * Author : WCH * Version : V1.0.0 - * Date : 2023/07/08 + * Date : 2024/10/30 * Description : Main Interrupt Service Routines. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } From 73ec4679812afa316c4b830f450ffb9c51717b4e Mon Sep 17 00:00:00 2001 From: Koki Mizumoto <21km43@gmail.com> Date: Sat, 11 Jan 2025 10:47:52 +0900 Subject: [PATCH 18/20] ch32x035 sdk update --- system/CH32X035/SRC/Core/core_riscv.c | 22 +- system/CH32X035/SRC/Core/core_riscv.h | 140 ++-- system/CH32X035/SRC/Debug/debug.c | 65 +- system/CH32X035/SRC/Debug/debug.h | 9 + system/CH32X035/SRC/Peripheral/inc/PIOC_SFR.h | 266 +++++++ system/CH32X035/SRC/Peripheral/inc/ch32x035.h | 749 ++++++++++++------ .../SRC/Peripheral/inc/ch32x035_adc.h | 2 +- .../SRC/Peripheral/inc/ch32x035_flash.h | 7 +- .../SRC/Peripheral/inc/ch32x035_gpio.h | 64 +- .../SRC/Peripheral/inc/ch32x035_i2c.h | 4 +- .../SRC/Peripheral/inc/ch32x035_misc.h | 47 +- .../SRC/Peripheral/inc/ch32x035_opa.h | 4 +- .../SRC/Peripheral/inc/ch32x035_pwr.h | 19 +- .../SRC/Peripheral/inc/ch32x035_spi.h | 7 +- .../SRC/Peripheral/inc/ch32x035_usb.h | 522 ++++++++++++ .../SRC/Peripheral/inc/ch32x035_usbpd.h | 412 ++++++++++ .../SRC/Peripheral/src/ch32x035_dbgmcu.c | 1 + .../SRC/Peripheral/src/ch32x035_flash.c | 301 ++++++- .../SRC/Peripheral/src/ch32x035_gpio.c | 252 ++++-- .../SRC/Peripheral/src/ch32x035_i2c.c | 6 +- .../SRC/Peripheral/src/ch32x035_misc.c | 60 +- .../SRC/Peripheral/src/ch32x035_opa.c | 3 +- .../SRC/Peripheral/src/ch32x035_pwr.c | 38 +- .../SRC/Peripheral/src/ch32x035_spi.c | 5 +- .../SRC/Peripheral/src/ch32x035_tim.c | 6 +- .../CH32X035/SRC/Startup/startup_ch32x035.S | 117 ++- system/CH32X035/USER/ch32x035_it.c | 6 +- 27 files changed, 2584 insertions(+), 550 deletions(-) create mode 100644 system/CH32X035/SRC/Peripheral/inc/PIOC_SFR.h create mode 100644 system/CH32X035/SRC/Peripheral/inc/ch32x035_usb.h create mode 100644 system/CH32X035/SRC/Peripheral/inc/ch32x035_usbpd.h diff --git a/system/CH32X035/SRC/Core/core_riscv.c b/system/CH32X035/SRC/Core/core_riscv.c index 46395d29..de160777 100644 --- a/system/CH32X035/SRC/Core/core_riscv.c +++ b/system/CH32X035/SRC/Core/core_riscv.c @@ -1,9 +1,9 @@ /********************************** (C) COPYRIGHT ******************************* * File Name : core_riscv.c * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : RISC-V Core Peripheral Access Layer Source File + * Version : V1.0.1 + * Date : 2023/11/11 + * Description : RISC-V V4 Core Peripheral Access Layer Source File for CH32X035 ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Attention: This software (modified or not) and binary are used for @@ -13,20 +13,20 @@ /* define compiler specific symbols */ #if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __ASM __asm /* asm keyword for ARM Compiler */ + #define __INLINE __inline /* inline keyword for ARM Compiler */ #elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + #define __ASM __asm /* asm keyword for IAR Compiler */ + #define __INLINE inline /* inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ #elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __ASM __asm /* asm keyword for GNU Compiler */ + #define __INLINE inline /* inline keyword for GNU Compiler */ #elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __ASM __asm /* asm keyword for TASKING Compiler */ + #define __INLINE inline /* inline keyword for TASKING Compiler */ #endif diff --git a/system/CH32X035/SRC/Core/core_riscv.h b/system/CH32X035/SRC/Core/core_riscv.h index d5197409..da67d65c 100644 --- a/system/CH32X035/SRC/Core/core_riscv.h +++ b/system/CH32X035/SRC/Core/core_riscv.h @@ -1,9 +1,9 @@ /********************************** (C) COPYRIGHT ******************************* * File Name : core_riscv.h * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : RISC-V Core Peripheral Access Layer Header File for CH32X035 + * Version : V1.0.1 + * Date : 2023/12/26 + * Description : RISC-V V4 Core Peripheral Access Layer Header File for CH32X035 ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Attention: This software (modified or not) and binary are used for @@ -22,8 +22,8 @@ extern "C" { #else #define __I volatile const /* defines 'read only' permissions */ #endif -#define __O volatile /* defines 'write only' permissions */ -#define __IO volatile /* defines 'read / write' permissions */ +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ /* Standard Peripheral Library old types (maintained for legacy purpose) */ typedef __I uint64_t vuc64; /* Read Only */ @@ -104,10 +104,10 @@ typedef struct{ /* memory mapped structure for SysTick */ typedef struct { - __IO u32 CTLR; - __IO u32 SR; - __IO u64 CNT; - __IO u64 CMP; + __IO uint32_t CTLR; + __IO uint32_t SR; + __IO uint64_t CNT; + __IO uint64_t CMP; }SysTick_Type; @@ -128,7 +128,7 @@ typedef struct */ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq() { - __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) ); + __asm volatile ("csrs 0x800, %0" : : "r" (0x88) ); } /********************************************************************* @@ -140,7 +140,7 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq() */ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq() { - __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) ); + __asm volatile ("csrc 0x800, %0" : : "r" (0x88) ); } /********************************************************************* @@ -184,7 +184,7 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Ty } /********************************************************************* - * @fn NVIC_GetStatusIRQ + * @fn NVIC_GetStatusIRQ * * @brief Get Interrupt Enable State * @@ -262,8 +262,13 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn * @brief Set Interrupt Priority * * @param IRQn - Interrupt Numbers - * priority: bit7 - pre-emption priority - * bit6-bit5 - subpriority + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * priority - bit[7] - Preemption Priority + * bit[6:5] - Sub priority + * bit[4:0] - Reserve + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * priority - bit[7:5] - Sub priority + * bit[4:0] - Reserve * * @return none */ @@ -286,7 +291,7 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) } /********************************************************************* - * @fn _SEV + * @fn _SEV * * @brief Set Event * @@ -302,7 +307,7 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void) } /********************************************************************* - * @fn _WFE + * @fn _WFE * * @brief Wait for Events * @@ -315,7 +320,7 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void) } /********************************************************************* - * @fn __WFE + * @fn __WFE * * @brief Wait for Events * @@ -334,13 +339,14 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) * @brief Set VTF Interrupt * * @param addr - VTF interrupt service function base address. - * IRQn - Interrupt Numbers - * num - VTF Interrupt Numbers - * NewState - DISABLE or ENABLE + * IRQn - Interrupt Numbers + * num - VTF Interrupt Numbers + * NewState - DISABLE or ENABLE * * @return none */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState) +{ if(num > 3) return ; if (NewState != DISABLE) @@ -348,7 +354,8 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr NVIC->VTFIDR[num] = IRQn; NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); } - else{ + else + { NVIC->VTFIDR[num] = IRQn; NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); } @@ -367,12 +374,13 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void) } /********************************************************************* - * @fn __AMOADD_W + * @fn __AMOADD_W * - * @brief Atomic Add with 32bit value - * Atomically ADD 32bit value with value in memory using amoadd.d. - * addr - Address pointer to data, address need to be 4byte aligned - * value - value to be ADDed + * @brief Atomic Add with 32bit value + * Atomically ADD 32bit value with value in memory using amoadd.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ADDed * * @return return memory value + add value */ @@ -388,10 +396,11 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile /********************************************************************* * @fn __AMOAND_W * - * @brief Atomic And with 32bit value - * Atomically AND 32bit value with value in memory using amoand.d. - * addr - Address pointer to data, address need to be 4byte aligned - * value - value to be ANDed + * @brief Atomic And with 32bit value + * Atomically AND 32bit value with value in memory using amoand.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ANDed * * @return return memory value & and value */ @@ -405,14 +414,15 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile } /********************************************************************* - * @fn __AMOMAX_W + * @fn __AMOMAX_W * - * @brief Atomic signed MAX with 32bit value - * @details Atomically signed max compare 32bit value with value in memory using amomax.d. - * addr - Address pointer to data, address need to be 4byte aligned - * value - value to be compared + * @brief Atomic signed MAX with 32bit value + * Atomically signed max compare 32bit value with value in memory using amomax.d. * - * @return the bigger value + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the bigger value */ __attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) { @@ -424,12 +434,13 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile } /********************************************************************* - * @fn __AMOMAXU_W + * @fn __AMOMAXU_W * - * @brief Atomic unsigned MAX with 32bit value - * Atomically unsigned max compare 32bit value with value in memory using amomaxu.d. - * addr - Address pointer to data, address need to be 4byte aligned - * value - value to be compared + * @brief Atomic unsigned MAX with 32bit value + * Atomically unsigned max compare 32bit value with value in memory using amomaxu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared * * @return return the bigger value */ @@ -445,10 +456,11 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatil /********************************************************************* * @fn __AMOMIN_W * - * @brief Atomic signed MIN with 32bit value - * Atomically signed min compare 32bit value with value in memory using amomin.d. - * addr - Address pointer to data, address need to be 4byte aligned - * value - value to be compared + * @brief Atomic signed MIN with 32bit value + * Atomically signed min compare 32bit value with value in memory using amomin.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared * * @return the smaller value */ @@ -466,10 +478,11 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile * * @brief Atomic unsigned MIN with 32bit value * Atomically unsigned min compare 32bit value with value in memory using amominu.d. - * addr - Address pointer to data, address need to be 4byte aligned + * + * @param addr - Address pointer to data, address need to be 4byte aligned * value - value to be compared * - * @return the smaller value + * @return the smaller value */ __attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) { @@ -481,12 +494,13 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatil } /********************************************************************* - * @fn __AMOOR_W + * @fn __AMOOR_W * - * @brief Atomic OR with 32bit value - * @details Atomically OR 32bit value with value in memory using amoor.d. - * addr - Address pointer to data, address need to be 4byte aligned - * value - value to be ORed + * @brief Atomic OR with 32bit value + * Atomically OR 32bit value with value in memory using amoor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ORed * * @return return memory value | and value */ @@ -500,13 +514,14 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile i } /********************************************************************* - * @fn __AMOSWAP_W + * @fn __AMOSWAP_W + * + * @brief Atomically swap new 32bit value into memory using amoswap.d. * - * @brief Atomically swap new 32bit value into memory using amoswap.d. - * addr - Address pointer to data, address need to be 4byte aligned - * newval - New value to be stored into the address + * @param addr - Address pointer to data, address need to be 4byte aligned + * newval - New value to be stored into the address * - * @return return the original value in memory + * @return return the original value in memory */ __attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) { @@ -520,10 +535,11 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatil /********************************************************************* * @fn __AMOXOR_W * - * @brief Atomic XOR with 32bit value - * @details Atomically XOR 32bit value with value in memory using amoxor.d. - * addr - Address pointer to data, address need to be 4byte aligned - * value - value to be XORed + * @brief Atomic XOR with 32bit value + * Atomically XOR 32bit value with value in memory using amoxor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be XORed * * @return return memory value ^ and value */ diff --git a/system/CH32X035/SRC/Debug/debug.c b/system/CH32X035/SRC/Debug/debug.c index a223d15f..0f083858 100644 --- a/system/CH32X035/SRC/Debug/debug.c +++ b/system/CH32X035/SRC/Debug/debug.c @@ -14,6 +14,10 @@ static uint8_t p_us = 0; static uint16_t p_ms = 0; + +#define DEBUG_DATA0_ADDRESS ((volatile uint32_t*)0xE0000380) +#define DEBUG_DATA1_ADDRESS ((volatile uint32_t*)0xE0000384) + /********************************************************************* * @fn Delay_Init * @@ -139,6 +143,22 @@ void USART_Printf_Init(uint32_t baudrate) #endif } +/********************************************************************* + * @fn SDI_Printf_Enable + * + * @brief Initializes the SDI printf Function. + * + * @param None + * + * @return None + */ +void SDI_Printf_Enable(void) +{ + *(DEBUG_DATA0_ADDRESS) = 0; + Delay_Init(); + Delay_Ms(1); +} + /********************************************************************* * @fn _write * @@ -149,12 +169,48 @@ void USART_Printf_Init(uint32_t baudrate) * * @return size - Data length */ -#if 0 __attribute__((used)) int _write(int fd, char *buf, int size) { - int i; + int i = 0; + +#if (SDI_PRINT == SDI_PR_OPEN) + int writeSize = size; + do + { + + /** + * data0 data1 ¹²8¸ö×Ö½Ú + * data0×îµÍλµÄ×Ö½Ú´æ·Å³¤¶È£¬×î´óΪ 7 + * + */ + + while( (*(DEBUG_DATA0_ADDRESS) != 0u)) + { + + } + + if(writeSize>7) + { + *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); + *(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); + + i += 7; + writeSize -= 7; + } + else + { + *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); + *(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); + + writeSize = 0; + } + + } while (writeSize); + + +#else for(i = 0; i < size; i++){ #if(DEBUG == DEBUG_UART1) while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); @@ -167,10 +223,9 @@ int _write(int fd, char *buf, int size) USART_SendData(USART3, *buf++); #endif } - +#endif return size; } -#endif /********************************************************************* * @fn _sbrk @@ -192,5 +247,3 @@ void *_sbrk(ptrdiff_t incr) curbrk += incr; return curbrk - incr; } -void _fini() {} -void _init() {} \ No newline at end of file diff --git a/system/CH32X035/SRC/Debug/debug.h b/system/CH32X035/SRC/Debug/debug.h index e1abcb0d..15e5846f 100644 --- a/system/CH32X035/SRC/Debug/debug.h +++ b/system/CH32X035/SRC/Debug/debug.h @@ -30,10 +30,19 @@ extern "C" { #define DEBUG DEBUG_UART1 #endif +/* SDI Printf Definition */ +#define SDI_PR_CLOSE 0 +#define SDI_PR_OPEN 1 + +#ifndef SDI_PRINT +#define SDI_PRINT SDI_PR_CLOSE +#endif + void Delay_Init(void); void Delay_Us(uint32_t n); void Delay_Ms(uint32_t n); void USART_Printf_Init(uint32_t baudrate); +void SDI_Printf_Enable(void); #if(DEBUG) #define PRINT(format, ...) printf(format, ##__VA_ARGS__) diff --git a/system/CH32X035/SRC/Peripheral/inc/PIOC_SFR.h b/system/CH32X035/SRC/Peripheral/inc/PIOC_SFR.h new file mode 100644 index 00000000..fcb81eae --- /dev/null +++ b/system/CH32X035/SRC/Peripheral/inc/PIOC_SFR.h @@ -0,0 +1,266 @@ +/* Define for PIOC */ +/* Website: http://wch.cn */ +/* Email: tech@wch.cn */ +/* Author: W.ch 2022.08 */ +/* V1.0 SpecialFunctionRegister */ + +// __PIOC_SFR_H__ + +#ifndef __PIOC_SFR_H__ +#define __PIOC_SFR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +// Register Bit Attribute / Bit Access Type +// RO: Read Only (internal change) +// RW: Read / Write +// Attribute: master/PIOC + +/* Register name rule: + R32_* for 32 bits register (UINT32,ULONG) + R16_* for 16 bits register (UINT16,USHORT) + R8_* for 8 bits register (UINT8,UCHAR) + RB_* for bit or bit mask of 8 bit register */ + +/* ********************************************************************************************************************* */ + +#define PIOC_SRAM_BASE (SRAM_BASE+0x4000) // PIOC code RAM base address + +#define PIOC_SFR_BASE PIOC_BASE // PIOC SFR base address + +#define R32_PIOC_SFR (*((volatile unsigned long *)(PIOC_SFR_BASE+0x04))) // RO/RW, PIOC SFR + +#define R8_INDIR_ADDR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x04))) // RO/RW, PIOC indirect address + +#define R8_TMR0_COUNT (*((volatile unsigned char *)(PIOC_SFR_BASE+0x05))) // RO/RW, PIOC timer count + +#define R8_TMR0_CTRL (*((volatile unsigned char *)(PIOC_SFR_BASE+0x06))) // RO/RW, PIOC timer control and GP bit +#define RB_EN_LEVEL1 0x80 // RO/RW, enable IO1 level change to wakeup & action interrupt flag +#define RB_EN_LEVEL0 0x40 // RO/RW, enable IO0 level change to wakeup & action interrupt flag +#define RB_GP_BIT_Y 0x20 // RO/RW, general-purpose bit 1, reset by power on, no effect if system reset or RB_MST_RESET reset +#define RB_GP_BIT_X 0x10 // RO/RW, general-purpose bit 0, reset by power on, no effect if system reset or RB_MST_RESET reset +#define RB_TMR0_MODE 0x08 // RO/RW, timer mode: 0-timer, 1-PWM +#define RB_TMR0_FREQ2 0x04 // RO/RW, timer clock frequency selection 2 +#define RB_TMR0_FREQ1 0x02 // RO/RW, timer clock frequency selection 1 +#define RB_TMR0_FREQ0 0x01 // RO/RW, timer clock frequency selection 0 + +#define R8_TMR0_INIT (*((volatile unsigned char *)(PIOC_SFR_BASE+0x07))) // RO/RW, PIOC timer initial value + + +#define R32_PORT_CFG (*((volatile unsigned long *)(PIOC_SFR_BASE+0x08))) // RO/RW, port status and config + +#define R8_BIT_CYCLE (*((volatile unsigned char *)(PIOC_SFR_BASE+0x08))) // RO/RW, encode bit cycle +#define RB_BIT_TX_O0 0x80 // RO/RW, bit data for IO0 port encode output +#define RB_BIT_CYCLE 0x7F // RO/RW, IO0 port bit data cycle -1 + +#define R8_INDIR_ADDR2 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x09))) // RO/RW, PIOC indirect address 2 + +#define R8_PORT_DIR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x0A))) // RO/RW, IO port direction and mode +//#define RB_PORT_MOD3 0x80 // RO/RW, IO port mode 3 +//#define RB_PORT_MOD2 0x40 // RO/RW, IO port mode 2 +//#define RB_PORT_MOD1 0x20 // RO/RW, IO port mode 1 +//#define RB_PORT_MOD0 0x10 // RO/RW, IO port mode 0 +//#define RB_PORT_PU1 0x08 // RO/RW, IO1 port pullup enable +//#define RB_PORT_PU0 0x04 // RO/RW, IO0 port pullup enable +#define RB_PORT_DIR1 0x02 // RO/RW, IO1 port direction +#define RB_PORT_DIR0 0x01 // RO/RW, IO0 port direction + +#define R8_PORT_IO (*((volatile unsigned char *)(PIOC_SFR_BASE+0x0B))) // RO/RW, IO port input and output +#define RB_PORT_IN_XOR 0x80 // RO/RO, IO0 XOR IO1 port input +#define RB_BIT_RX_I0 0x40 // RO/RO, decoced bit data for IO0 port received +#define RB_PORT_IN1 0x20 // RO/RO, IO1 port input +#define RB_PORT_IN0 0x10 // RO/RO, IO0 port input +#define RB_PORT_XOR1 0x08 // RO/RO, IO1 port output XOR input +#define RB_PORT_XOR0 0x04 // RO/RO, IO0 port output XOR input +#define RB_PORT_OUT1 0x02 // RO/RW, IO1 port output +#define RB_PORT_OUT0 0x01 // RO/RW, IO0 port output + + +#define R32_DATA_CTRL (*((volatile unsigned long *)(PIOC_SFR_BASE+0x1C))) // RW/RW, data control + +#define R8_SYS_CFG (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1C))) // RW/RW, port config +#define RB_INT_REQ 0x80 // RO/RW, PIOC interrupt request action, set 1/0 by PIOC, clear 0 by master write R8_CTRL_RD (no effect) +#define RB_DATA_SW_MR 0x40 // RO/RO, R8_CTRL_RD wait for read status, set 1 by PIOC write R8_CTRL_RD, clear 0 by master read R8_CTRL_RD +#define RB_DATA_MW_SR 0x20 // RO/RO, R8_CTRL_WR wait for read status, set 1 by master write R8_CTRL_WR, clear 0 by PIOC read R8_CTRL_WR +#define RB_MST_CFG_B4 0x10 // RW/RO, config inform bit, default 0 +#define RB_MST_IO_EN1 0x08 // RW/RO, IO1 switch enable, default 0 +#define RB_MST_IO_EN0 0x04 // RW/RO, IO0 switch enable, default 0 +#define RB_MST_RESET 0x02 // RW/RO, force PIOC reset, high action, default 0 +#define RB_MST_CLK_GATE 0x01 // RW/RO, PIOC global clock enable, high action, default 0 + +#define R8_CTRL_RD (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1D))) // RO/RW, data for master read only and PIOC write only + +#define R8_CTRL_WR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1E))) // RW/RO, data for master write only and PIOC read only + +#define R8_DATA_EXCH (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1F))) // RW/RW, data exchange + + +#define R32_DATA_REG0_3 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x20))) // RW/RW, data buffer 0~3 +#define R8_DATA_REG0 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x20))) // RW/RW, data buffer 0 +#define R8_DATA_REG1 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x21))) // RW/RW, data buffer 1 +#define R8_DATA_REG2 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x22))) // RW/RW, data buffer 2 +#define R8_DATA_REG3 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x23))) // RW/RW, data buffer 3 + +#define R32_DATA_REG4_7 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x24))) // RW/RW, data buffer 4~7 +#define R8_DATA_REG4 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x24))) // RW/RW, data buffer 4 +#define R8_DATA_REG5 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x25))) // RW/RW, data buffer 5 +#define R8_DATA_REG6 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x26))) // RW/RW, data buffer 6 +#define R8_DATA_REG7 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x27))) // RW/RW, data buffer 7 + +#define R32_DATA_REG8_11 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x28))) // RW/RW, data buffer 8~11 +#define R8_DATA_REG8 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x28))) // RW/RW, data buffer 8 +#define R8_DATA_REG9 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x29))) // RW/RW, data buffer 9 +#define R8_DATA_REG10 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2A))) // RW/RW, data buffer 10 +#define R8_DATA_REG11 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2B))) // RW/RW, data buffer 11 + +#define R32_DATA_REG12_15 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x2C))) // RW/RW, data buffer 12~15 +#define R8_DATA_REG12 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2C))) // RW/RW, data buffer 12 +#define R8_DATA_REG13 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2D))) // RW/RW, data buffer 13 +#define R8_DATA_REG14 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2E))) // RW/RW, data buffer 14 +#define R8_DATA_REG15 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2F))) // RW/RW, data buffer 15 + +#define R32_DATA_REG16_19 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x30))) // RW/RW, data buffer 16~19 +#define R8_DATA_REG16 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x30))) // RW/RW, data buffer 16 +#define R8_DATA_REG17 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x31))) // RW/RW, data buffer 17 +#define R8_DATA_REG18 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x32))) // RW/RW, data buffer 18 +#define R8_DATA_REG19 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x33))) // RW/RW, data buffer 19 + +#define R32_DATA_REG20_23 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x34))) // RW/RW, data buffer 20~23 +#define R8_DATA_REG20 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x34))) // RW/RW, data buffer 20 +#define R8_DATA_REG21 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x35))) // RW/RW, data buffer 21 +#define R8_DATA_REG22 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x36))) // RW/RW, data buffer 22 +#define R8_DATA_REG23 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x37))) // RW/RW, data buffer 23 + +#define R32_DATA_REG24_27 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x38))) // RW/RW, data buffer 24~27 +#define R8_DATA_REG24 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x38))) // RW/RW, data buffer 24 +#define R8_DATA_REG25 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x39))) // RW/RW, data buffer 25 +#define R8_DATA_REG26 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3A))) // RW/RW, data buffer 26 +#define R8_DATA_REG27 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3B))) // RW/RW, data buffer 27 + +#define R32_DATA_REG28_31 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x3C))) // RW/RW, data buffer 28~31 +#define R8_DATA_REG28 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3C))) // RW/RW, data buffer 28 +#define R8_DATA_REG29 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3D))) // RW/RW, data buffer 29 +#define R8_DATA_REG30 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3E))) // RW/RW, data buffer 30 +#define R8_DATA_REG31 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3F))) // RW/RW, data buffer 31 + +/* ******************************************************************************************************* */ + +/* PIOC Registers */ +typedef struct +{ + uint32_t RESERVED00; + union { + __IO uint32_t D32_PIOC_SFR ; // RO/RW, PIOC SFR + struct { + __IO uint8_t D8_INDIR_ADDR; // RO/RW, PIOC indirect address + __IO uint8_t D8_TMR0_COUNT; // RO/RW, PIOC timer count + __IO uint8_t D8_TMR0_CTRL; // RO/RW, PIOC timer control and GP bit + __IO uint8_t D8_TMR0_INIT; // RO/RW, PIOC timer initial value + } ; + } ; + union { + __IO uint32_t D32_PORT_CFG ; // RO/RW, port status and config + struct { + __IO uint8_t D8_BIT_CYCLE; // RO/RW, encode bit cycle + __IO uint8_t D8_INDIR_ADDR2; // RO/RW, PIOC indirect address 2 + __IO uint8_t D8_PORT_DIR; // RO/RW, IO port direction and mode + __IO uint8_t D8_PORT_IO; // RO/RW, IO port input and output + } ; + } ; + uint32_t RESERVED0C; + uint32_t RESERVED10; + uint32_t RESERVED14; + uint32_t RESERVED18; + union { + __IO uint32_t D32_DATA_CTRL ; // RW/RW, data control + struct { + __IO uint8_t D8_SYS_CFG; // RW/RW, port config + __IO uint8_t D8_CTRL_RD; // RO/RW, data for master read only and PIOC write only + __IO uint8_t D8_CTRL_WR; // RW/RO, data for master write only and PIOC read only + __IO uint8_t D8_DATA_EXCH; // RW/RW, data exchange + } ; + } ; + union { + __IO uint32_t D32_DATA_REG0_3 ; // RW/RW, data buffer 0~3 + struct { + __IO uint8_t D8_DATA_REG0; // RW/RW, data buffer 0 + __IO uint8_t D8_DATA_REG1; // RW/RW, data buffer 1 + __IO uint8_t D8_DATA_REG2; // RW/RW, data buffer 2 + __IO uint8_t D8_DATA_REG3; // RW/RW, data buffer 3 + } ; + __IO uint16_t D16_DATA_REG0_1 ; // RW/RW, data buffer 0~1 + } ; + union { + __IO uint32_t D32_DATA_REG4_7 ; // RW/RW, data buffer 4~7 + struct { + __IO uint8_t D8_DATA_REG4; // RW/RW, data buffer 4 + __IO uint8_t D8_DATA_REG5; // RW/RW, data buffer 5 + __IO uint8_t D8_DATA_REG6; // RW/RW, data buffer 6 + __IO uint8_t D8_DATA_REG7; // RW/RW, data buffer 7 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG8_11 ; // RW/RW, data buffer 8~11 + struct { + __IO uint8_t D8_DATA_REG8; // RW/RW, data buffer 8 + __IO uint8_t D8_DATA_REG9; // RW/RW, data buffer 9 + __IO uint8_t D8_DATA_REG10; // RW/RW, data buffer 10 + __IO uint8_t D8_DATA_REG11; // RW/RW, data buffer 11 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG12_15 ; // RW/RW, data buffer 12~15 + struct { + __IO uint8_t D8_DATA_REG12; // RW/RW, data buffer 12 + __IO uint8_t D8_DATA_REG13; // RW/RW, data buffer 13 + __IO uint8_t D8_DATA_REG14; // RW/RW, data buffer 14 + __IO uint8_t D8_DATA_REG15; // RW/RW, data buffer 15 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG16_19 ; // RW/RW, data buffer 16~19 + struct { + __IO uint8_t D8_DATA_REG16; // RW/RW, data buffer 16 + __IO uint8_t D8_DATA_REG17; // RW/RW, data buffer 17 + __IO uint8_t D8_DATA_REG18; // RW/RW, data buffer 18 + __IO uint8_t D8_DATA_REG19; // RW/RW, data buffer 19 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG20_23 ; // RW/RW, data buffer 20~23 + struct { + __IO uint8_t D8_DATA_REG20; // RW/RW, data buffer 20 + __IO uint8_t D8_DATA_REG21; // RW/RW, data buffer 21 + __IO uint8_t D8_DATA_REG22; // RW/RW, data buffer 22 + __IO uint8_t D8_DATA_REG23; // RW/RW, data buffer 23 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG24_27 ; // RW/RW, data buffer 24~27 + struct { + __IO uint8_t D8_DATA_REG24; // RW/RW, data buffer 24 + __IO uint8_t D8_DATA_REG25; // RW/RW, data buffer 25 + __IO uint8_t D8_DATA_REG26; // RW/RW, data buffer 26 + __IO uint8_t D8_DATA_REG27; // RW/RW, data buffer 27 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG28_31 ; // RW/RW, data buffer 28~31 + struct { + __IO uint8_t D8_DATA_REG28; // RW/RW, data buffer 28 + __IO uint8_t D8_DATA_REG29; // RW/RW, data buffer 29 + __IO uint8_t D8_DATA_REG30; // RW/RW, data buffer 30 + __IO uint8_t D8_DATA_REG31; // RW/RW, data buffer 31 + } ; + } ; +} PIOC_TypeDef; + +#define PIOC ((PIOC_TypeDef *)PIOC_BASE) + +#ifdef __cplusplus +} +#endif + +#endif // __PIOC_SFR_H__ diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035.h index a5c889a8..3f4501c9 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035.h @@ -1,8 +1,8 @@ /********************************** (C) COPYRIGHT ******************************* * File Name : ch32x035.h * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 + * Version : V1.0.1 + * Date : 2024/10/28 * Description : CH32X035 Device Peripheral Access Layer Header File. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -23,7 +23,7 @@ extern "C" { /* Standard Peripheral Library version number */ #define __STDPERIPH_VERSION_MAIN (0x01) /* [15:8] main version */ -#define __STDPERIPH_VERSION_SUB (0x00) /* [7:0] sub version */ +#define __STDPERIPH_VERSION_SUB (0x08) /* [7:0] sub version */ #define __STDPERIPH_VERSION ((__STDPERIPH_VERSION_MAIN << 8)\ |(__STDPERIPH_VERSION_SUB << 0)) @@ -37,7 +37,7 @@ typedef enum IRQn Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ - SysTicK_IRQn = 12, /* 12 System timer Interrupt */ + SysTick_IRQn = 12, /* 12 System timer Interrupt */ Software_IRQn = 14, /* 14 software Interrupt */ /****** RISC-V specific Interrupt Numbers *********************************************************/ @@ -82,6 +82,7 @@ typedef enum IRQn } IRQn_Type; #define HardFault_IRQn EXC_IRQn +#define SysTicK_IRQn SysTick_IRQn #include #include "core_riscv.h" @@ -305,14 +306,42 @@ typedef struct uint16_t RESERVED11; __IO uint16_t RPTCR; uint16_t RESERVED12; - __IO uint16_t CH1CVR; - uint16_t RESERVED13; - __IO uint16_t CH2CVR; - uint16_t RESERVED14; - __IO uint16_t CH3CVR; - uint16_t RESERVED15; - __IO uint16_t CH4CVR; - uint16_t RESERVED16; + union + { + __IO uint32_t CH1CVR_R32; + struct + { + __IO uint16_t CH1CVR; + uint16_t RESERVED13; + }; + }; + union + { + __IO uint32_t CH2CVR__R32; + struct + { + __IO uint16_t CH2CVR; + uint16_t RESERVED14; + }; + }; + union + { + __IO uint32_t CH3CVR__R32; + struct + { + __IO uint16_t CH3CVR; + uint16_t RESERVED15; + }; + }; + union + { + __IO uint32_t CH4CVR__R32; + struct + { + __IO uint16_t CH4CVR; + uint16_t RESERVED16; + }; + }; __IO uint16_t BDTR; uint16_t RESERVED17; __IO uint16_t DMACFGR; @@ -669,12 +698,11 @@ typedef struct #define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ /******************* Bit definition for ADC_CTLR1 register ********************/ -#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH ((uint32_t)0x0000000F) /* AWDCH[3:0] bits (Analog watchdog channel select bits) */ #define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ #define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ #define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ #define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ #define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ #define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ @@ -690,20 +718,13 @@ typedef struct #define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ #define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ -#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ -#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ -#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ -#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ - #define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ #define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ +#define ADC_TKENABLE ((uint32_t)0x01000000) /* TKEN mode enable */ /******************* Bit definition for ADC_CTLR2 register ********************/ #define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ #define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ -#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ -#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ #define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ #define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ @@ -722,7 +743,6 @@ typedef struct #define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ #define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ #define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ -#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ /****************** Bit definition for ADC_SAMPTR1 register *******************/ #define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ @@ -1002,7 +1022,31 @@ typedef struct /******************** Bit definition for ADC_RDATAR register ********************/ #define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ -#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ + +/******************** Bit definition for ADC_CTLR3 register ********************/ +#define ADC_CTLR3_CLK_DIV ((uint32_t)0x0000000F) /* CLK_DIVL[3:0] bits */ +#define ADC_CTLR3_CLK_DIV_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_CTLR3_CLK_DIV_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_CTLR3_CLK_DIV_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_CTLR3_CLK_DIV_3 ((uint32_t)0x00000008) /* Bit 3 */ + +#define ADC_CTLR3_AWD_SCAN ((uint32_t)0x00000200) /* Analog watchdog Scan enable */ +#define ADC_CTLR3_AWD0_RST_EN ((uint32_t)0x00001000) /* Watchdog0 Reset Enable */ +#define ADC_CTLR3_AWD1_RST_EN ((uint32_t)0x00002000) /* Watchdog1 Reset Enable */ +#define ADC_CTLR3_AWD2_RST_EN ((uint32_t)0x00004000) /* Watchdog2 Reset Enable */ +#define ADC_CTLR3_AWD3_RST_EN ((uint32_t)0x00008000) /* Watchdog3 Reset Enable */ + +/******************** Bit definition for ADC_WDTR1 register ********************/ +#define ADC_WDTR1_LTR1 ((uint32_t)0x00000FFF) /* Analog watchdog1 low threshold */ +#define ADC_WDTR1_HTR1 ((uint32_t)0x0FFF0000) /* Analog watchdog1 high threshold */ + +/******************** Bit definition for ADC_WDTR2 register ********************/ +#define ADC_WDTR2_LTR2 ((uint32_t)0x00000FFF) /* Analog watchdog2 low threshold */ +#define ADC_WDTR2_HTR2 ((uint32_t)0x0FFF0000) /* Analog watchdog2 high threshold */ + +/******************** Bit definition for ADC_WDTR3 register ********************/ +#define ADC_WDTR3_LTR3 ((uint32_t)0x00000FFF) /* Analog watchdog3 low threshold */ +#define ADC_WDTR3_HTR3 ((uint32_t)0x0FFF0000) /* Analog watchdog3 high threshold */ /******************************************************************************/ /* DMA Controller */ @@ -1554,27 +1598,33 @@ typedef struct /****************** Bit definition for FLASH_STATR register *******************/ #define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ -#define FLASH_STATR_PGERR ((uint8_t)0x04) /* Programming Error */ + #define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ #define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ +#define FLASH_STATR_FWAKE_FLAG ((uint8_t)0x40) /* Flag of wake */ +#define FLASH_STATR_TURBO ((uint8_t)0x80) /* The state of TURBO Enable */ +#define FLASH_STATR_BOOT_AVA ((uint16_t)0x1000) /* The state of Init Config */ +#define FLASH_STATR_BOOT_STATUS ((uint16_t)0x2000) /* The source of Execute Program */ +#define FLASH_STATR_BOOT_MODE ((uint16_t)0x4000) /* The switch of user section or boot section*/ +#define FLASH_STATR_BOOT_LOCK ((uint16_t)0x8000) /* Lock boot area*/ /******************* Bit definition for FLASH_CTLR register *******************/ -#define FLASH_CTLR_PG ((uint32_t)0x00000001) /* Programming */ #define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Sector Erase 4K */ #define FLASH_CTLR_MER ((uint32_t)0x00000004) /* Mass Erase */ #define FLASH_CTLR_OPTPG ((uint32_t)0x00000010) /* Option Byte Programming */ #define FLASH_CTLR_OPTER ((uint32_t)0x00000020) /* Option Byte Erase */ #define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */ #define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */ -#define FLASH_CTLR_OPTWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_OBWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */ #define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */ #define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */ -#define FLASH_CTLR_FAST_LOCK ((uint32_t)0x00008000) /* Fast Lock */ -#define FLASH_CTLR_PAGE_PG ((uint32_t)0x00010000) /* Page Programming 256Byte */ -#define FLASH_CTLR_PAGE_ER ((uint32_t)0x00020000) /* Page Erase 256Byte */ -#define FLASH_CTLR_PAGE_BER32 ((uint32_t)0x00040000) /* Block Erase 32K */ -#define FLASH_CTLR_PAGE_BER64 ((uint32_t)0x00080000) /* Block Erase 64K */ -#define FLASH_CTLR_PG_STRT ((uint32_t)0x00200000) /* Page Programming Start */ +#define FLASH_CTLR_FWAKEIE ((uint32_t)0x00002000) /* Wake inter Enable */ +#define FLASH_CTLR_FLOCK ((uint32_t)0x00008000) /* Fast Lock */ +#define FLASH_CTLR_FTPG ((uint32_t)0x00010000) /* Fast Program */ +#define FLASH_CTLR_FTER ((uint32_t)0x00020000) /* Fast Erase */ +#define FLASH_CTLR_BUFLOAD ((uint32_t)0x00040000) /* BUF Load */ +#define FLASH_CTLR_BUFRST ((uint32_t)0x00080000) /* BUF Reset */ +#define FLASH_CTLR_BER32 ((uint32_t)0x00800000) /* Block Erase 32K */ /******************* Bit definition for FLASH_ADDR register *******************/ #define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ @@ -1583,15 +1633,29 @@ typedef struct #define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ #define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ -#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ +#define FLASH_OBR_USER ((uint16_t)0x007C) /* User Option Bytes */ #define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ #define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ #define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ -#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /* BFB2 */ +#define FLASH_OBR_CFGRSTT ((uint16_t)0x0060) /* Config Reset delay time */ + +#define FLASH_OBR_FIX_11 ((uint16_t)0x0300) /* fix 11 */ +#define FLASH_OBR_DATA0 ((uint32_t)0x0003FC00) /* Data byte0 */ +#define FLASH_OBR_DATA1 ((uint32_t)0x03FC0000) /* Data byte1 */ /****************** Bit definition for FLASH_WPR register ******************/ #define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ +/****************** Bit definition for FLASH_MODEKEYR register ******************/ +#define FLASH_MODEKEYR_MODEKEYR ((uint32_t)0xFFFFFFFF) /* Open fast program /erase */ +#define FLASH_MODEKEYR_MODEKEYR1 ((uint32_t)0x45670123) +#define FLASH_MODEKEYR_MODEKEYR2 ((uint32_t)0xCDEF89AB) + +/****************** Bit definition for BOOT_MODEKEYP register ******************/ +#define BOOT_MODEKEYP_MODEKEYR ((uint32_t)0xFFFFFFFF) /* Open Boot section */ +#define BOOT_MODEKEYP_MODEKEYR1 ((uint32_t)0x45670123) +#define BOOT_MODEKEYP_MODEKEYR2 ((uint32_t)0xCDEF89AB) + /****************** Bit definition for FLASH_RDPR register *******************/ #define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ #define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ @@ -1783,6 +1847,14 @@ typedef struct #define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ #define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ #define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ +#define GPIO_INDR_IDR16 ((uint32_t)0x10000) /* Port input data, bit 16 */ +#define GPIO_INDR_IDR17 ((uint32_t)0x20000) /* Port input data, bit 17 */ +#define GPIO_INDR_IDR18 ((uint32_t)0x40000) /* Port input data, bit 18 */ +#define GPIO_INDR_IDR19 ((uint32_t)0x80000) /* Port input data, bit 19 */ +#define GPIO_INDR_IDR20 ((uint32_t)0x100000) /* Port input data, bit 20 */ +#define GPIO_INDR_IDR21 ((uint32_t)0x200000) /* Port input data, bit 21 */ +#define GPIO_INDR_IDR22 ((uint32_t)0x400000) /* Port input data, bit 22 */ +#define GPIO_INDR_IDR23 ((uint32_t)0x800000) /* Port input data, bit 23 */ /******************* Bit definition for GPIO_OUTDR register *******************/ #define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ @@ -1801,6 +1873,14 @@ typedef struct #define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ #define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ #define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ +#define GPIO_OUTDR_ODR16 ((uint32_t)0x10000) /* Port output data, bit 16 */ +#define GPIO_OUTDR_ODR17 ((uint32_t)0x20000) /* Port output data, bit 17 */ +#define GPIO_OUTDR_ODR18 ((uint32_t)0x40000) /* Port output data, bit 18 */ +#define GPIO_OUTDR_ODR19 ((uint32_t)0x80000) /* Port output data, bit 19 */ +#define GPIO_OUTDR_ODR20 ((uint32_t)0x100000) /* Port output data, bit 20 */ +#define GPIO_OUTDR_ODR21 ((uint32_t)0x200000) /* Port output data, bit 21 */ +#define GPIO_OUTDR_ODR22 ((uint32_t)0x400000) /* Port output data, bit 22 */ +#define GPIO_OUTDR_ODR23 ((uint32_t)0x800000) /* Port output data, bit 23 */ /****************** Bit definition for GPIO_BSHR register *******************/ #define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ @@ -1854,6 +1934,15 @@ typedef struct #define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ #define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ #define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ +#define GPIO_BCR_BR16 ((uint32_t)0x10000) /* Port x Reset bit 16 */ +#define GPIO_BCR_BR17 ((uint32_t)0x20000) /* Port x Reset bit 17 */ +#define GPIO_BCR_BR18 ((uint32_t)0x40000) /* Port x Reset bit 18 */ +#define GPIO_BCR_BR19 ((uint32_t)0x80000) /* Port x Reset bit 19 */ +#define GPIO_BCR_BR20 ((uint32_t)0x100000) /* Port x Reset bit 20 */ +#define GPIO_BCR_BR21 ((uint32_t)0x200000) /* Port x Reset bit 21 */ +#define GPIO_BCR_BR22 ((uint32_t)0x400000) /* Port x Reset bit 22 */ +#define GPIO_BCR_BR23 ((uint32_t)0x800000) /* Port x Reset bit 23 */ + /****************** Bit definition for GPIO_LCKR register *******************/ #define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ @@ -1872,190 +1961,299 @@ typedef struct #define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ #define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ #define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ -#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ +#define GPIO_LCK16 ((uint32_t)0x00010000) /* Port x Lock bit 16 */ +#define GPIO_LCK17 ((uint32_t)0x00020000) /* Port x Lock bit 17 */ +#define GPIO_LCK18 ((uint32_t)0x00040000) /* Port x Lock bit 18 */ +#define GPIO_LCK19 ((uint32_t)0x00080000) /* Port x Lock bit 19 */ +#define GPIO_LCK20 ((uint32_t)0x00100000) /* Port x Lock bit 20 */ +#define GPIO_LCK21 ((uint32_t)0x00200000) /* Port x Lock bit 21 */ +#define GPIO_LCK22 ((uint32_t)0x00400000) /* Port x Lock bit 22 */ +#define GPIO_LCK23 ((uint32_t)0x00800000) /* Port x Lock bit 23 */ + +#define GPIO_LCKK ((uint32_t)0x01000000) /* Lock key */ + +/******************* Bit definition for GPIO_CFGXR register *******************/ +#define GPIO_CFGXR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGXR_MODE16 ((uint32_t)0x00000003) /* MODE16[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGXR_MODE16_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGXR_MODE16_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGXR_MODE17 ((uint32_t)0x00000030) /* MODE17[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGXR_MODE17_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGXR_MODE17_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGXR_MODE18 ((uint32_t)0x00000300) /* MODE18[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGXR_MODE18_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGXR_MODE18_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGXR_MODE19 ((uint32_t)0x00003000) /* MODE19[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGXR_MODE19_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGXR_MODE19_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGXR_MODE20 ((uint32_t)0x00030000) /* MODE20[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGXR_MODE20_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGXR_MODE20_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGXR_MODE21 ((uint32_t)0x00300000) /* MODE21[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGXR_MODE21_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGXR_MODE21_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGXR_MODE22 ((uint32_t)0x03000000) /* MODE22[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGXR_MODE22_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGXR_MODE22_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGXR_MODE23 ((uint32_t)0x30000000) /* MODE23[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGXR_MODE23_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGXR_MODE23_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGXR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGXR_CNF16 ((uint32_t)0x0000000C) /* CNF16[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGXR_CNF16_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGXR_CNF16_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGXR_CNF17 ((uint32_t)0x000000C0) /* CNF17[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGXR_CNF17_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGXR_CNF17_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGXR_CNF18 ((uint32_t)0x00000C00) /* CNF18[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGXR_CNF18_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGXR_CNF18_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGXR_CNF19 ((uint32_t)0x0000C000) /* CNF19[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGXR_CNF19_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGXR_CNF19_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGXR_CNF20 ((uint32_t)0x000C0000) /* CNF20[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGXR_CNF20_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGXR_CNF20_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGXR_CNF21 ((uint32_t)0x00C00000) /* CNF21[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGXR_CNF21_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGXR_CNF21_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGXR_CNF22 ((uint32_t)0x0C000000) /* CNF22[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGXR_CNF22_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGXR_CNF22_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGXR_CNF23 ((uint32_t)0xC0000000) /* CNF23[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGXR_CNF23_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGXR_CNF23_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/****************** Bit definition for GPIO_BSXR register *******************/ +#define GPIO_BSXR_BS16 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSXR_BS17 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSXR_BS18 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSXR_BS19 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSXR_BS20 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSXR_BS21 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSXR_BS22 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSXR_BS23 ((uint32_t)0x00000080) /* Port x Set bit 7 */ + +#define GPIO_BSXR_BR16 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSXR_BR17 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSXR_BR18 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSXR_BR19 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSXR_BR20 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSXR_BR21 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSXR_BR22 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSXR_BR23 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ /****************** Bit definition for AFIO_PCFR1register *******************/ -#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ -#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ -#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ -#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */ +#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000003) /* SPI1_REMAP[1:0] bits (SPI1 remapping) */ +#define AFIO_PCFR1_SPI1_REMAP_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define AFIO_PCFR1_SPI1_REMAP_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x0000001C) /* I2C1_REMAP[4:2] bits (I2C1 remapping) */ +#define AFIO_PCFR1_I2C1_REMAP_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define AFIO_PCFR1_I2C1_REMAP_1 ((uint32_t)0x00000008) /* Bit 1 */ +#define AFIO_PCFR1_I2C1_REMAP_2 ((uint32_t)0x00000010) /* Bit 2 */ -#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ +#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000060) /* USART1_REMAP[6:5] bits (USART1 remapping) */ +#define AFIO_PCFR1_USART1_REMAP_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define AFIO_PCFR1_USART1_REMAP_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000380) /* USART2_REMAP[9:7] bits (USART2 remapping) */ +#define AFIO_PCFR1_USART2_REMAP_0 ((uint32_t)0x00000080) /* Bit 0 */ +#define AFIO_PCFR1_USART2_REMAP_1 ((uint32_t)0x00000100) /* Bit 1 */ +#define AFIO_PCFR1_USART2_REMAP_2 ((uint32_t)0x00000200) /* Bit 2 */ -#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ +#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000C00) /* USART3_REMAP[11:10] bits (USART3 remapping) */ +#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define AFIO_PCFR1_USART4_REMAP ((uint32_t)0x00007000) /* USART4_REMAP[14:12] bits (USART4 remapping) */ +#define AFIO_PCFR1_USART4_REMAP_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define AFIO_PCFR1_USART4_REMAP_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define AFIO_PCFR1_USART4_REMAP_2 ((uint32_t)0x00004000) /* Bit 2 */ -#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ +#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x00038000) /* TIM1_REMAP[17:15] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define AFIO_PCFR1_TIM1_REMAP_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x001C0000) /* TIM2_REMAP[20:18] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define AFIO_PCFR1_TIM2_REMAP_2 ((uint32_t)0x00100000) /* Bit 2 */ -#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ +#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00600000) /* TIM3_REMAP[22:21] bits (TIM3 remapping) */ +#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00400000) /* Bit 1 */ + +#define AFIO_PCFR1_PIOC_REMAP ((uint32_t)0x00800000) /* PIOC[23] bits (PIOC remapping) */ #define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ #define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ #define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ #define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ -#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ - /***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ - -#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ - -#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ - -#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ - -#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI0 ((uint32_t)0x00000003) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint32_t)0x0000000C) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000030) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint32_t)0x000000C0) /* EXTI 3 configuration */ +#define AFIO_EXTICR1_EXTI4 ((uint32_t)0x00000300) /* EXTI 4 configuration */ +#define AFIO_EXTICR1_EXTI5 ((uint32_t)0x00000C00) /* EXTI 5 configuration */ +#define AFIO_EXTICR1_EXTI6 ((uint32_t)0x00003000) /* EXTI 6 configuration */ +#define AFIO_EXTICR1_EXTI7 ((uint32_t)0x0000C000) /* EXTI 7 configuration */ +#define AFIO_EXTICR1_EXTI8 ((uint32_t)0x00030000) /* EXTI 8 configuration */ +#define AFIO_EXTICR1_EXTI9 ((uint32_t)0x000C0000) /* EXTI 9 configuration */ +#define AFIO_EXTICR1_EXTI10 ((uint32_t)0x00300000) /* EXTI 10 configuration */ +#define AFIO_EXTICR1_EXTI11 ((uint32_t)0x00C00000) /* EXTI 11 configuration */ +#define AFIO_EXTICR1_EXTI12 ((uint32_t)0x03000000) /* EXTI 12 configuration */ +#define AFIO_EXTICR1_EXTI13 ((uint32_t)0x0C000000) /* EXTI 13 configuration */ +#define AFIO_EXTICR1_EXTI14 ((uint32_t)0x30000000) /* EXTI 14 configuration */ +#define AFIO_EXTICR1_EXTI15 ((uint32_t)0xC0000000) /* EXTI 15 configuration */ + +#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /* PC[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000004) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000008) /* PC[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000010) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000020) /* PC[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00000040) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00000080) /* PC[3] pin */ + +#define AFIO_EXTICR1_EXTI4_PA ((uint32_t)0x00000000) /* PA[4] pin */ +#define AFIO_EXTICR1_EXTI4_PB ((uint32_t)0x00000100) /* PB[4] pin */ +#define AFIO_EXTICR1_EXTI4_PC ((uint32_t)0x00000200) /* PC[4] pin */ + +#define AFIO_EXTICR1_EXTI5_PA ((uint32_t)0x00000000) /* PA[5] pin */ +#define AFIO_EXTICR1_EXTI5_PB ((uint32_t)0x00000400) /* PB[5] pin */ +#define AFIO_EXTICR1_EXTI5_PC ((uint32_t)0x00000800) /* PC[5] pin */ + +#define AFIO_EXTICR1_EXTI6_PA ((uint32_t)0x00000000) /* PA[6] pin */ +#define AFIO_EXTICR1_EXTI6_PB ((uint32_t)0x00001000) /* PB[6] pin */ +#define AFIO_EXTICR1_EXTI6_PC ((uint32_t)0x00002000) /* PC[6] pin */ + +#define AFIO_EXTICR1_EXTI7_PA ((uint32_t)0x00000000) /* PA[7] pin */ +#define AFIO_EXTICR1_EXTI7_PB ((uint32_t)0x00004000) /* PB[7] pin */ +#define AFIO_EXTICR1_EXTI7_PC ((uint32_t)0x00008000) /* PC[7] pin */ + +#define AFIO_EXTICR1_EXTI8_PA ((uint32_t)0x00000000) /* PA[8] pin */ +#define AFIO_EXTICR1_EXTI8_PB ((uint32_t)0x00010000) /* PB[8] pin */ +#define AFIO_EXTICR1_EXTI8_PC ((uint32_t)0x00020000) /* PC[8] pin */ + +#define AFIO_EXTICR1_EXTI9_PA ((uint32_t)0x00000000) /* PA[9] pin */ +#define AFIO_EXTICR1_EXTI9_PB ((uint32_t)0x00040000) /* PB[9] pin */ +#define AFIO_EXTICR1_EXTI9_PC ((uint32_t)0x00080000) /* PC[9] pin */ + +#define AFIO_EXTICR1_EXTI10_PA ((uint32_t)0x00000000) /* PA[10] pin */ +#define AFIO_EXTICR1_EXTI10_PB ((uint32_t)0x00100000) /* PB[10] pin */ +#define AFIO_EXTICR1_EXTI10_PC ((uint32_t)0x00200000) /* PC[10] pin */ + +#define AFIO_EXTICR1_EXTI11_PA ((uint32_t)0x00000000) /* PA[11] pin */ +#define AFIO_EXTICR1_EXTI11_PB ((uint32_t)0x00400000) /* PB[11] pin */ +#define AFIO_EXTICR1_EXTI11_PC ((uint32_t)0x00800000) /* PC[11] pin */ + +#define AFIO_EXTICR1_EXTI12_PA ((uint32_t)0x00000000) /* PA[12] pin */ +#define AFIO_EXTICR1_EXTI12_PB ((uint32_t)0x01000000) /* PB[12] pin */ +#define AFIO_EXTICR1_EXTI12_PC ((uint32_t)0x02000000) /* PC[12] pin */ + +#define AFIO_EXTICR1_EXTI13_PA ((uint32_t)0x00000000) /* PA[13] pin */ +#define AFIO_EXTICR1_EXTI13_PB ((uint32_t)0x04000000) /* PB[13] pin */ +#define AFIO_EXTICR1_EXTI13_PC ((uint32_t)0x08000000) /* PC[13] pin */ + +#define AFIO_EXTICR1_EXTI14_PA ((uint32_t)0x00000000) /* PA[14] pin */ +#define AFIO_EXTICR1_EXTI14_PB ((uint32_t)0x10000000) /* PB[14] pin */ +#define AFIO_EXTICR1_EXTI14_PC ((uint32_t)0x20000000) /* PC[14] pin */ + +#define AFIO_EXTICR1_EXTI15_PA ((uint32_t)0x00000000) /* PA[15] pin */ +#define AFIO_EXTICR1_EXTI15_PB ((uint32_t)0x40000000) /* PB[15] pin */ +#define AFIO_EXTICR1_EXTI15_PC ((uint32_t)0x80000000) /* PC[15] pin */ /***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ - -#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ -#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /* PE[4] pin */ -#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /* PF[4] pin */ -#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /* PG[4] pin */ - -#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ -#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /* PE[5] pin */ -#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /* PF[5] pin */ -#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /* PG[5] pin */ - -#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ -#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /* PE[6] pin */ -#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /* PF[6] pin */ -#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /* PG[6] pin */ - -#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ -#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /* PE[7] pin */ -#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /* PF[7] pin */ -#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /* PG[7] pin */ - -/***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ - -#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ -#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /* PE[8] pin */ -#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /* PF[8] pin */ -#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /* PG[8] pin */ - -#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ -#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /* PE[9] pin */ -#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /* PF[9] pin */ -#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /* PG[9] pin */ - -#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ -#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /* PE[10] pin */ -#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /* PF[10] pin */ -#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /* PG[10] pin */ - -#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ -#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /* PE[11] pin */ -#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /* PF[11] pin */ -#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /* PG[11] pin */ - -/***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ - -#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ -#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /* PE[12] pin */ -#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /* PF[12] pin */ -#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /* PG[12] pin */ - -#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ -#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /* PE[13] pin */ -#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /* PF[13] pin */ -#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /* PG[13] pin */ - -#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ -#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /* PE[14] pin */ -#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /* PF[14] pin */ -#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /* PG[14] pin */ - -#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ -#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /* PE[15] pin */ -#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /* PF[15] pin */ -#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /* PG[15] pin */ +#define AFIO_EXTICR2_EXTI16 ((uint32_t)0x00000003) /* EXTI 16 configuration */ +#define AFIO_EXTICR2_EXTI17 ((uint32_t)0x0000000C) /* EXTI 17 configuration */ +#define AFIO_EXTICR2_EXTI18 ((uint32_t)0x00000030) /* EXTI 18 configuration */ +#define AFIO_EXTICR2_EXTI19 ((uint32_t)0x000000C0) /* EXTI 19 configuration */ +#define AFIO_EXTICR2_EXTI20 ((uint32_t)0x00000300) /* EXTI 20 configuration */ +#define AFIO_EXTICR2_EXTI21 ((uint32_t)0x00000C00) /* EXTI 21 configuration */ +#define AFIO_EXTICR2_EXTI22 ((uint32_t)0x00003000) /* EXTI 22 configuration */ +#define AFIO_EXTICR2_EXTI23 ((uint32_t)0x0000C000) /* EXTI 23 configuration */ + +#define AFIO_EXTICR2_EXTI16_PA ((uint32_t)0x00000000) /* PA[16] pin */ +#define AFIO_EXTICR2_EXTI16_PB ((uint32_t)0x00000001) /* PB[16] pin */ +#define AFIO_EXTICR2_EXTI16_PC ((uint32_t)0x00000002) /* PC[16] pin */ + +#define AFIO_EXTICR2_EXTI17_PA ((uint32_t)0x00000000) /* PA[17] pin */ +#define AFIO_EXTICR2_EXTI17_PB ((uint32_t)0x00000004) /* PB[17] pin */ +#define AFIO_EXTICR2_EXTI17_PC ((uint32_t)0x00000008) /* PC[17] pin */ + +#define AFIO_EXTICR2_EXTI18_PA ((uint32_t)0x00000000) /* PA[18] pin */ +#define AFIO_EXTICR2_EXTI18_PB ((uint32_t)0x00000010) /* PB[18] pin */ +#define AFIO_EXTICR2_EXTI18_PC ((uint32_t)0x00000020) /* PC[18] pin */ + +#define AFIO_EXTICR2_EXTI19_PA ((uint32_t)0x00000000) /* PA[19] pin */ +#define AFIO_EXTICR2_EXTI19_PB ((uint32_t)0x00000040) /* PB[19] pin */ +#define AFIO_EXTICR2_EXTI19_PC ((uint32_t)0x00000080) /* PC[19] pin */ + +#define AFIO_EXTICR2_EXTI20_PA ((uint32_t)0x00000000) /* PA[20] pin */ +#define AFIO_EXTICR2_EXTI20_PB ((uint32_t)0x00000100) /* PB[20] pin */ +#define AFIO_EXTICR2_EXTI20_PC ((uint32_t)0x00000200) /* PC[20] pin */ + +#define AFIO_EXTICR2_EXTI21_PA ((uint32_t)0x00000000) /* PA[21] pin */ +#define AFIO_EXTICR2_EXTI21_PB ((uint32_t)0x00000400) /* PB[21] pin */ +#define AFIO_EXTICR2_EXTI21_PC ((uint32_t)0x00000800) /* PC[21] pin */ + +#define AFIO_EXTICR2_EXTI22_PA ((uint32_t)0x00000000) /* PA[22] pin */ +#define AFIO_EXTICR2_EXTI22_PB ((uint32_t)0x00001000) /* PB[22] pin */ +#define AFIO_EXTICR2_EXTI22_PC ((uint32_t)0x00002000) /* PC[22] pin */ + +#define AFIO_EXTICR2_EXTI23_PA ((uint32_t)0x00000000) /* PA[23] pin */ +#define AFIO_EXTICR2_EXTI23_PB ((uint32_t)0x00004000) /* PB[23] pin */ +#define AFIO_EXTICR2_EXTI23_PC ((uint32_t)0x00008000) /* PC[23] pin */ + +/******************* Bit definition for AFIO_CTLR register ********************/ +#define AFIO_CTLR_UDM_PUE ((uint32_t)0x00000003) /* PC16/UDM Pin pull-up Mode*/ +#define AFIO_CTLR_UDM_PUE_0 ((uint32_t)0x00000001) /* bit[0] */ +#define AFIO_CTLR_UDM_PUE_1 ((uint32_t)0x00000002) /* bit[1] */ + +#define AFIO_CTLR_UDP_PUE ((uint32_t)0x0000000C) /* PC17/UDP Pin pull-up Mode*/ +#define AFIO_CTLR_UDP_PUE_0 ((uint32_t)0x00000004) /* bit[2] */ +#define AFIO_CTLR_UDP_PUE_1 ((uint32_t)0x00000008) /* bit[3] */ + +#define AFIO_CTLR_USB_PHY_V33 ((uint32_t)0x00000040) /* USB transceiver PHY output and pull-up limiter configuration */ +#define AFIO_CTLR_USB_IOEN ((uint32_t)0x00000080) /* USB Remap pin enable */ +#define AFIO_CTLR_USBPD_PHY_V33 ((uint32_t)0x00000100) /* USBPD transceiver PHY output and pull-up limiter configuration */ +#define AFIO_CTLR_USBPD_IN_HVT ((uint32_t)0x00000200) /* PD pin PC14/PC15 high threshold input mode */ +#define AFIO_CTLR_UDP_BC_VSRC ((uint32_t)0x00010000) /* PC17/UDP pin BC protocol source voltage enable */ +#define AFIO_CTLR_UDM_BC_VSRC ((uint32_t)0x00020000) /* PC16/UDM pin BC protocol source voltage enable */ +#define AFIO_CTLR_UDP_BC_CMPO ((uint32_t)0x00040000) /* PC17/UDP pin BC protocol comparator status */ +#define AFIO_CTLR_UDM_BC_CMPO ((uint32_t)0x00080000) /* PC16/UDM pin BC protocol comparator status */ +#define AFIO_CTLR_PA3_FILT_EN ((uint32_t)0x01000000) /* Controls the input filtering of the PA3 pin */ +#define AFIO_CTLR_PA4_FILT_EN ((uint32_t)0x02000000) /* Controls the input filtering of the PA4 pin */ +#define AFIO_CTLR_PB5_FILT_EN ((uint32_t)0x04000000) /* Controls the input filtering of the PB5 pin */ +#define AFIO_CTLR_PB6_FILT_EN ((uint32_t)0x08000000) /* Controls the input filtering of the PB6 pin */ /******************************************************************************/ /* Independent WATCHDOG */ @@ -2083,8 +2281,6 @@ typedef struct /******************* Bit definition for I2C_CTLR1 register ********************/ #define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ -#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ -#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ #define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ #define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ #define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ @@ -2094,7 +2290,7 @@ typedef struct #define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ #define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ #define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ -#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ + #define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ /******************* Bit definition for I2C_CTLR2 register ********************/ @@ -2149,16 +2345,12 @@ typedef struct #define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ #define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ #define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ -#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ -#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ /******************* Bit definition for I2C_STAR2 register ********************/ #define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ #define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ #define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ #define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ -#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ -#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ #define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ #define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ @@ -2173,20 +2365,24 @@ typedef struct /******************** Bit definition for PWR_CTLR register ********************/ #define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ -#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ -#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS ((uint16_t)0x0060) /* PLS[2:0] bits (PVD Level Selection) */ #define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ #define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ -#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ -#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ +#define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000) /* PVD level 0 */ +#define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020) /* PVD level 1 */ +#define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040) /* PVD level 2 */ +#define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060) /* PVD level 3 */ + +#define PWR_CTLR_LP_REG ((uint16_t)0x0200) /* Software configure flash into lower energy mode */ +#define PWR_CTLR_LP ((uint16_t)0x0C00) /* Software configure flash Status */ +#define PWR_CTLR_LP_0 ((uint16_t)0x0400) +#define PWR_CTLR_LP_1 ((uint16_t)0x0800) /******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ -#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ #define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ -#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ +#define PWR_CSR_Flash_ack ((uint16_t)0x0200) /* Flash Status */ /******************************************************************************/ /* Reset and Clock Control */ @@ -2284,6 +2480,11 @@ typedef struct #define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ #define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ +/******************* Bit definition for RCC_AHBRSTR register ********************/ +#define RCC_USBFSRST ((uint32_t)0x00001000) /* USBFS reset */ +#define RCC_PIOCRST ((uint32_t)0x00002000) /* PIOC RST */ +#define RCC_USBPDRST ((uint32_t)0x00020000) /* USBPD reset */ + /******************************************************************************/ /* Serial Peripheral Interface */ /******************************************************************************/ @@ -2316,6 +2517,7 @@ typedef struct #define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ #define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ #define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ +#define SPI_CTLR2_ODEN ((uint16_t)0x8000) /* SPI OD output Enable */ /******************** Bit definition for SPI_STATR register ********************/ #define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ @@ -2339,32 +2541,8 @@ typedef struct /****************** Bit definition for SPI_TCRCR register ******************/ #define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ -/****************** Bit definition for SPI_I2SCFGR register *****************/ -#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /* Channel length (number of bits per audio channel) */ - -#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */ -#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /* Bit 0 */ -#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /* Bit 1 */ - -#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /* steady state clock polarity */ - -#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */ -#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /* Bit 0 */ -#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /* Bit 1 */ - -#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /* PCM frame synchronization */ - -#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */ -#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /* Bit 0 */ -#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /* I2S Enable */ -#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /* I2S mode selection */ - -/****************** Bit definition for SPI_I2SPR register *******************/ -#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /* I2S Linear prescaler */ -#define SPI_I2SPR_ODD ((uint16_t)0x0100) /* Odd factor for the prescaler */ -#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /* Master Clock Output Enable */ +/****************** Bit definition for SPI_HSCR register *****************/ +#define SPI_HSCR_HSRXEN ((uint16_t)0x0001) /* Read Enable under SPI High speed mode */ /******************************************************************************/ /* TIM */ @@ -2387,6 +2565,10 @@ typedef struct #define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ #define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_CMP_BK ((uint16_t)0x1000) /* voltage comparator break enable, TIM1 only */ +#define TIM_CAPOV ((uint16_t)0x4000) /* Cfg mode of capture value */ +#define TIM_CAPLVL ((uint16_t)0x8000) + /******************* Bit definition for TIM_CTLR2 register ********************/ #define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ #define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ @@ -2586,7 +2768,6 @@ typedef struct #define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ #define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ #define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ -#define TIM_CC4NP ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */ /******************* Bit definition for TIM_CNT register ********************/ #define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ @@ -2602,15 +2783,19 @@ typedef struct /******************* Bit definition for TIM_CH1CVR register *******************/ #define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ +#define TIM_LEVEL1 ((uint32_t)0x00010000) /******************* Bit definition for TIM_CH2CVR register *******************/ #define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ +#define TIM_LEVEL2 ((uint32_t)0x00010000) /******************* Bit definition for TIM_CH3CVR register *******************/ #define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ +#define TIM_LEVEL3 ((uint32_t)0x00010000) /******************* Bit definition for TIM_CH4CVR register *******************/ #define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ +#define TIM_LEVEL4 ((uint32_t)0x00010000) /******************* Bit definition for TIM_BDTR register *******************/ #define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ @@ -2652,6 +2837,15 @@ typedef struct /******************* Bit definition for TIM_DMAADR register *******************/ #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ +/******************* Bit definition for TIM_SPEC register *******************/ +#define TIM_SPEC_PWM_EN_1_2 ((uint16_t)0x0001) /* Channel 1 and Channel 2 alternate */ +#define TIM_SPEC_PWM_EN_3_4 ((uint16_t)0x0002) /* Channel 3 and Channel 4 alternate */ +#define TIM_SPEC_PWM_OC1 ((uint16_t)0x0010) /* Channel 1 invalid level under alternate mode */ +#define TIM_SPEC_PWM_OC2 ((uint16_t)0x0020) /* Channel 2 invalid level under alternate mode */ +#define TIM_SPEC_PWM_OC3 ((uint16_t)0x0040) /* Channel 3 invalid level under alternate mode */ +#define TIM_SPEC_PWM_OC4 ((uint16_t)0x0080) /* Channel 4 invalid level under alternate mode */ +#define TIM_SPEC_TOGGLE ((uint16_t)0x8000) /* valid channel indicator */ + /******************************************************************************/ /* Universal Synchronous Asynchronous Receiver Transmitter */ /******************************************************************************/ @@ -2690,7 +2884,6 @@ typedef struct #define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ #define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ #define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ -#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /* USART Oversmapling 8-bits */ /****************** Bit definition for USART_CTLR2 register *******************/ #define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ @@ -2719,7 +2912,6 @@ typedef struct #define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ #define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ #define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ -#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */ /****************** Bit definition for USART_GPR register ******************/ #define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ @@ -2769,6 +2961,77 @@ typedef struct /******************* Bit definition for WWDG_STATR register ********************/ #define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ +/******************************************************************************/ +/* OPA and CMP */ +/******************************************************************************/ + +/******************* Bit definition for OPA_CFGR1 register ********************/ +#define OPA_CFGR1_POLL_EN1 ((uint16_t)0x0001) +#define OPA_CFGR1_POLL_EN2 ((uint16_t)0x0002) +#define OPA_CFGR1_BKIN_EN1 ((uint16_t)0x0004) +#define OPA_CFGR1_BKIN_EN2 ((uint16_t)0x0008) +#define OPA_CFGR1_RST_EN1 ((uint16_t)0x0010) +#define OPA_CFGR1_RST_EN2 ((uint16_t)0x0020) +#define OPA_CFGR1_BKIN_SEL ((uint16_t)0x0040) +#define OPA_CFGR1_POLL_LOCK ((uint16_t)0x0080) +#define OPA_CFGR1_IE_OUT1 ((uint16_t)0x0100) +#define OPA_CFGR1_IE_OUT2 ((uint16_t)0x0200) +#define OPA_CFGR1_IE_CNT ((uint16_t)0x0400) +#define OPA_CFGR1_NMI_EN ((uint16_t)0x0800) +#define OPA_CFGR1_IF_OUT1 ((uint16_t)0x1000) +#define OPA_CFGR1_IF_OUT2 ((uint16_t)0x2000) +#define OPA_CFGR1_IF_CNT ((uint16_t)0x4000) + +/******************* Bit definition for OPA_CFGR2 register ********************/ +#define OPA_CFGR2_POLL_VLU ((uint16_t)0x01FF) +#define OPA_CFGR2_POLL1_NUM ((uint16_t)0x0600) +#define OPA_CFGR2_POLL2_NUM ((uint16_t)0x1800) + +/******************* Bit definition for OPA_CTLR1 register ********************/ +#define OPA_CTLR1_EN1 ((uint32_t)0x00000001) +#define OPA_CTLR1_MODE1 ((uint32_t)0x00000002) + +#define OPA_CTLR1_PSEL1 ((uint32_t)0x00000018) + +#define OPA_CTLR1_FB_EN1 ((uint32_t)0x00000020) +#define OPA_CTLR1_NSEL1 ((uint32_t)0x000001C0) + +#define OPA_CTLR1_EN2 ((uint32_t)0x00010000) +#define OPA_CTLR1_MODE2 ((uint32_t)0x00020000) + +#define OPA_CTLR1_PSEL2 ((uint32_t)0x00180000) + +#define OPA_CTLR1_FB_EN2 ((uint32_t)0x00200000) +#define OPA_CTLR1_NSEL2 ((uint32_t)0x01C00000) + +#define OPA_CTLR1_OPA_LOCK ((uint32_t)0x80000000) + +/******************* Bit definition for OPA_CTLR2 register ********************/ +#define OPA_CTLR2_EN1 ((uint32_t)0x00000001) +#define OPA_CTLR2_MODE1 ((uint32_t)0x00000002) +#define OPA_CTLR2_NSEL1 ((uint32_t)0x00000004) +#define OPA_CTLR2_PSEL1 ((uint32_t)0x00000008) + +#define OPA_CTLR2_EN2 ((uint32_t)0x00000020) +#define OPA_CTLR2_MODE2 ((uint32_t)0x00000040) +#define OPA_CTLR2_NSEL2 ((uint32_t)0x00000080) +#define OPA_CTLR2_PSEL2 ((uint32_t)0x00000100) + +#define OPA_CTLR2_EN3 ((uint32_t)0x00000400) +#define OPA_CTLR2_MODE3 ((uint32_t)0x00000800) +#define OPA_CTLR2_NSEL3 ((uint32_t)0x00001000) +#define OPA_CTLR2_PSEL3 ((uint32_t)0x00002000) + +#define OPA_CTLR2_CMP_LOCK ((uint32_t)0x00002000) + +/******************* Bit definition for OPA_KEY register ********************/ +#define OPA_KEY ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for CMP_KEY register ********************/ +#define CMP_KEY ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for POLL_KEY register ********************/ +#define POLL_KEY ((uint32_t)0xFFFFFFFF) #include "ch32x035_conf.h" diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_adc.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_adc.h index d3be07bc..ec71306b 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_adc.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_adc.h @@ -39,7 +39,7 @@ typedef struct can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. - This parameter can be a value of @ref ADC_data_align */ + This parameter can be a value of @ref ADC_data_align, Note:ADC_DataAlign_Left only applies to regular channels */ uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted using the sequencer for regular channel group. diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_flash.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_flash.h index e6b1ce2f..13bfa969 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_flash.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_flash.h @@ -27,7 +27,10 @@ typedef enum FLASH_ERROR_WRP, FLASH_COMPLETE, FLASH_TIMEOUT, - FLASH_RDP + FLASH_RDP, + FLASH_OP_RANGE_ERROR = 0xFD, + FLASH_ALIGN_ERROR = 0xFE, + FLASH_ADR_RANGE_ERROR = 0xFF, } FLASH_Status; /* Flash_Latency */ @@ -135,6 +138,8 @@ void FLASH_BufLoad(uint32_t Address, uint32_t Data0); void FLASH_ErasePage_Fast(uint32_t Page_Address); void FLASH_ProgramPage_Fast(uint32_t Page_Address); void SystemReset_StartMode(uint32_t Mode); +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length); +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length); #ifdef __cplusplus diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_gpio.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_gpio.h index c788e281..d648110d 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_gpio.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_gpio.h @@ -2,7 +2,7 @@ * File Name : ch32x035_gpio.h * Author : WCH * Version : V1.0.0 - * Date : 2023/04/06 + * Date : 2023/12/26 * Description : This file contains all the functions prototypes for the * GPIO firmware library. ********************************************************************************* @@ -32,9 +32,7 @@ typedef enum GPIO_Mode_IN_FLOATING = 0x04, GPIO_Mode_IPD = 0x28, /* Only PA0--PA15 and PC16--PC17 support input pull-down */ GPIO_Mode_IPU = 0x48, - GPIO_Mode_Out_OD = 0x14, GPIO_Mode_Out_PP = 0x10, - GPIO_Mode_AF_OD = 0x1C, GPIO_Mode_AF_PP = 0x18 } GPIOMode_TypeDef; @@ -90,39 +88,39 @@ typedef enum #define GPIO_PartialRemap1_SPI1 ((uint32_t)0x00100001) /* SPI1 Partial1 Alternate Function mapping */ #define GPIO_PartialRemap2_SPI1 ((uint32_t)0x00100002) /* SPI1 Partial2 Alternate Function mapping */ #define GPIO_FullRemap_SPI1 ((uint32_t)0x00100003) /* SPI1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_I2C1 ((uint32_t)0x08000004) /* I2C1 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_I2C1 ((uint32_t)0x08000008) /* I2C1 Partial2 Alternate Function mapping */ -#define GPIO_PartialRemap3_I2C1 ((uint32_t)0x0800000C) /* I2C1 Partial3 Alternate Function mapping */ -#define GPIO_PartialRemap4_I2C1 ((uint32_t)0x08000010) /* I2C1 Partial4 Alternate Function mapping */ -#define GPIO_FullRemap_I2C1 ((uint32_t)0x08000014) /* I2C1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_I2C1 ((uint32_t)0x08020004) /* I2C1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_I2C1 ((uint32_t)0x08020008) /* I2C1 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_I2C1 ((uint32_t)0x0802000C) /* I2C1 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_I2C1 ((uint32_t)0x08020010) /* I2C1 Partial4 Alternate Function mapping */ +#define GPIO_FullRemap_I2C1 ((uint32_t)0x08020014) /* I2C1 Full Alternate Function mapping */ #define GPIO_PartialRemap1_USART1 ((uint32_t)0x00150020) /* USART1 Partial1 Alternate Function mapping */ #define GPIO_PartialRemap2_USART1 ((uint32_t)0x00150040) /* USART1 Partial2 Alternate Function mapping */ #define GPIO_FullRemap_USART1 ((uint32_t)0x00150060) /* USART1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_USART2 ((uint32_t)0x08000080) /* USART2 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_USART2 ((uint32_t)0x08000100) /* USART2 Partial2 Alternate Function mapping */ -#define GPIO_PartialRemap3_USART2 ((uint32_t)0x08000180) /* USART2 Partial3 Alternate Function mapping */ -#define GPIO_FullRemap_USART2 ((uint32_t)0x08000200) /* USART2 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_USART3 ((uint32_t)0x00100400) /* USART3 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_USART3 ((uint32_t)0x00100800) /* USART3 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_USART3 ((uint32_t)0x00100C00) /* USART3 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_USART4 ((uint32_t)0x08001000) /* USART4 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_USART4 ((uint32_t)0x08002000) /* USART4 Partial2 Alternate Function mapping */ -#define GPIO_PartialRemap3_USART4 ((uint32_t)0x08003000) /* USART4 Partial3 Alternate Function mapping */ -#define GPIO_PartialRemap4_USART4 ((uint32_t)0x08004000) /* USART4 Partial4 Alternate Function mapping */ -#define GPIO_FullRemap_USART4 ((uint32_t)0x08007000) /* USART4 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM1 ((uint32_t)0x08400001) /* TIM1 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM1 ((uint32_t)0x08400002) /* TIM1 Partial2 Alternate Function mapping */ -#define GPIO_PartialRemap3_TIM1 ((uint32_t)0x08400003) /* TIM1 Partial3 Alternate Function mapping */ -#define GPIO_FullRemap_TIM1 ((uint32_t)0x08400004) /* TIM1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x08200004) /* TIM2 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x08200008) /* TIM2 Partial2 Alternate Function mapping */ -#define GPIO_PartialRemap3_TIM2 ((uint32_t)0x0820000C) /* TIM2 Partial3 Alternate Function mapping */ -#define GPIO_PartialRemap4_TIM2 ((uint32_t)0x08200010) /* TIM2 Partial4 Alternate Function mapping */ -#define GPIO_PartialRemap5_TIM2 ((uint32_t)0x08200014) /* TIM2 Partial5 Alternate Function mapping */ -#define GPIO_FullRemap_TIM2 ((uint32_t)0x08200018) /* TIM2 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM3 ((uint32_t)0x00300020) /* TIM3 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM3 ((uint32_t)0x00300040) /* TIM3 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_TIM3 ((uint32_t)0x00300060) /* TIM3 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART2 ((uint32_t)0x08070080) /* USART2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART2 ((uint32_t)0x08070100) /* USART2 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_USART2 ((uint32_t)0x08070180) /* USART2 Partial3 Alternate Function mapping */ +#define GPIO_FullRemap_USART2 ((uint32_t)0x08070200) /* USART2 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART3 ((uint32_t)0x001A0400) /* USART3 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART3 ((uint32_t)0x001A0800) /* USART3 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x001A0C00) /* USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART4 ((uint32_t)0x080C1000) /* USART4 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART4 ((uint32_t)0x080C2000) /* USART4 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_USART4 ((uint32_t)0x080C3000) /* USART4 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_USART4 ((uint32_t)0x080C4000) /* USART4 Partial4 Alternate Function mapping */ +#define GPIO_FullRemap_USART4 ((uint32_t)0x080C7000) /* USART4 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM1 ((uint32_t)0x084F0001) /* TIM1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM1 ((uint32_t)0x084F0002) /* TIM1 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_TIM1 ((uint32_t)0x084F0003) /* TIM1 Partial3 Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x084F0004) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x08220004) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x08220008) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_TIM2 ((uint32_t)0x0822000C) /* TIM2 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_TIM2 ((uint32_t)0x08220010) /* TIM2 Partial4 Alternate Function mapping */ +#define GPIO_PartialRemap5_TIM2 ((uint32_t)0x08220014) /* TIM2 Partial5 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x08220018) /* TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM3 ((uint32_t)0x00350020) /* TIM3 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM3 ((uint32_t)0x00350040) /* TIM3 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x00350060) /* TIM3 Full Alternate Function mapping */ #define GPIO_Remap_PIOC ((uint32_t)0x00200080) /* PIOC Alternate Function mapping */ #define GPIO_Remap_SWJ_Disable ((uint32_t)0x08300400) /* SDI Disabled (SDI) */ diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_i2c.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_i2c.h index 37e29db4..fd0d0292 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_i2c.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_i2c.h @@ -98,14 +98,14 @@ typedef struct #define I2C_IT_ADDR ((uint32_t)0x02000002) #define I2C_IT_SB ((uint32_t)0x02000001) -/* SR2 register flags */ +/* STAR2 register flags */ #define I2C_FLAG_DUALF ((uint32_t)0x00800000) #define I2C_FLAG_GENCALL ((uint32_t)0x00100000) #define I2C_FLAG_TRA ((uint32_t)0x00040000) #define I2C_FLAG_BUSY ((uint32_t)0x00020000) #define I2C_FLAG_MSL ((uint32_t)0x00010000) -/* SR1 register flags */ +/* STAR1 register flags */ #define I2C_FLAG_PECERR ((uint32_t)0x10001000) #define I2C_FLAG_OVR ((uint32_t)0x10000800) #define I2C_FLAG_AF ((uint32_t)0x10000400) diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_misc.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_misc.h index aeda03c6..82390ccb 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_misc.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_misc.h @@ -2,7 +2,7 @@ * File Name : ch32x035_misc.h * Author : WCH * Version : V1.0.0 - * Date : 2023/04/06 + * Date : 2023/12/26 * Description : This file contains all the functions prototypes for the * miscellaneous firmware library functions. ********************************************************************************* @@ -19,21 +19,48 @@ extern "C" { #include "ch32x035.h" -/* NVIC Init Structure definition */ +/* CSR_INTSYSCR_INEST_definition */ +#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ + +/* Check the configuration of CSR(0x804) in the startup file(.S) + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * priority - bit[7] - Preemption Priority + * bit[6:5] - Sub priority + * bit[4:0] - Reserve + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * priority - bit[7:5] - Sub priority + * bit[4:0] - Reserve + */ + +#ifndef INTSYSCR_INEST +#define INTSYSCR_INEST INTSYSCR_INEST_EN +#endif + +/* NVIC Init Structure definition + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 7. + * + */ typedef struct { - uint8_t NVIC_IRQChannel; - uint8_t NVIC_IRQChannelPreemptionPriority; - uint8_t NVIC_IRQChannelSubPriority; + uint8_t NVIC_IRQChannel; + uint8_t NVIC_IRQChannelPreemptionPriority; + uint8_t NVIC_IRQChannelSubPriority; FunctionalState NVIC_IRQChannelCmd; } NVIC_InitTypeDef; /* Preemption_Priority_Group */ -#define NVIC_PriorityGroup_0 ((uint32_t)0x00) -#define NVIC_PriorityGroup_1 ((uint32_t)0x01) -#define NVIC_PriorityGroup_2 ((uint32_t)0x02) -#define NVIC_PriorityGroup_3 ((uint32_t)0x03) -#define NVIC_PriorityGroup_4 ((uint32_t)0x04) +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#else +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ +#endif void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct); diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_opa.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_opa.h index 1a022362..e408a6bd 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_opa.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_opa.h @@ -159,8 +159,8 @@ typedef enum /* CMP_out_channel_enumeration */ typedef enum { - OUT_IO_TIM2_CH1 = 0, - OUT_IO_PA1 + OUT_IO_TIM2 = 0, + OUT_IO0 } CMP_Mode_TypeDef; /* CMP_NSEL_enumeration */ diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_pwr.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_pwr.h index 9c734c4a..6dade485 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_pwr.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_pwr.h @@ -2,7 +2,7 @@ * File Name : ch32x035_pwr.h * Author : WCH * Version : V1.0.0 - * Date : 2023/04/06 + * Date : 2024/06/14 * Description : This file contains all the functions prototypes for the PWR * firmware library. ********************************************************************************* @@ -20,10 +20,15 @@ extern "C" { #include "ch32x035.h" /* PVD_detection_level */ -#define PWR_PVDLevel_2V1 ((uint32_t)0x00000000) -#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) -#define PWR_PVDLevel_3V0 ((uint32_t)0x00000040) -#define PWR_PVDLevel_4V0 ((uint32_t)0x00000060) +#define PWR_PVDLevel_0 ((uint32_t)0x00000000) +#define PWR_PVDLevel_1 ((uint32_t)0x00000020) +#define PWR_PVDLevel_2 ((uint32_t)0x00000040) +#define PWR_PVDLevel_3 ((uint32_t)0x00000060) + +#define PWR_PVDLevel_2V1 PWR_PVDLevel_0 +#define PWR_PVDLevel_2V3 PWR_PVDLevel_1 +#define PWR_PVDLevel_3V0 PWR_PVDLevel_2 +#define PWR_PVDLevel_4V0 PWR_PVDLevel_3 /* STOP_mode_entry */ #define PWR_STOPEntry_WFI ((uint8_t)0x01) @@ -33,11 +38,15 @@ extern "C" { #define PWR_FLAG_PVDO ((uint32_t)0x00000004) #define PWR_FLAG_FLASH ((uint32_t)0x00000020) +/* PWR_VDD_Supply_Voltage */ +typedef enum {PWR_VDD_5V = 0, PWR_VDD_3V3 = !PWR_VDD_5V} PWR_VDD; + void PWR_DeInit(void); void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); void PWR_EnterSTOPMode(uint8_t PWR_STOPEntry); void PWR_EnterSTANDBYMode(void); FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +PWR_VDD PWR_VDD_SupplyVoltage(void); #ifdef __cplusplus } diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_spi.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_spi.h index 27f624c3..24d61a1c 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_spi.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_spi.h @@ -2,7 +2,7 @@ * File Name : ch32x035_spi.h * Author : WCH * Version : V1.0.0 - * Date : 2023/04/06 + * Date : 2024/06/05 * Description : This file contains all the functions prototypes for the * SPI firmware library. ********************************************************************************* @@ -32,7 +32,8 @@ typedef struct This parameter can be a value of @ref SPI_data_size */ uint16_t SPI_CPOL; /* Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ + This parameter can be a value of @ref SPI_Clock_Polarity + When using SPI slave mode to send data, the CPOL bit should be set to 1 */ uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_Clock_Phase */ @@ -69,7 +70,7 @@ typedef struct /* SPI_Clock_Polarity */ #define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) +#define SPI_CPOL_High ((uint16_t)0x0002)//When using SPI slave mode to send data, the CPOL bit should be set to 1. /* SPI_Clock_Phase */ #define SPI_CPHA_1Edge ((uint16_t)0x0000) diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_usb.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_usb.h new file mode 100644 index 00000000..76d326c1 --- /dev/null +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_usb.h @@ -0,0 +1,522 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_usb.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/08/02 + * Description : This file contains all the functions prototypes for the USB + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_USB_H +#define __CH32X035_USB_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +/*******************************************************************************/ +/* Header File */ +#include "stdint.h" + +/*******************************************************************************/ +/* USB Communication Related Macro Definition */ + +/* USB PID */ +#ifndef USB_PID_SETUP +#define USB_PID_NULL 0x00 +#define USB_PID_SOF 0x05 +#define USB_PID_SETUP 0x0D +#define USB_PID_IN 0x09 +#define USB_PID_OUT 0x01 +#define USB_PID_NYET 0x06 +#define USB_PID_ACK 0x02 +#define USB_PID_NAK 0x0A +#define USB_PID_STALL 0x0E +#define USB_PID_DATA0 0x03 +#define USB_PID_DATA1 0x0B +#define USB_PID_PRE 0x0C +#endif + +/* USB standard device request code */ +#ifndef USB_GET_DESCRIPTOR +#define USB_GET_STATUS 0x00 +#define USB_CLEAR_FEATURE 0x01 +#define USB_SET_FEATURE 0x03 +#define USB_SET_ADDRESS 0x05 +#define USB_GET_DESCRIPTOR 0x06 +#define USB_SET_DESCRIPTOR 0x07 +#define USB_GET_CONFIGURATION 0x08 +#define USB_SET_CONFIGURATION 0x09 +#define USB_GET_INTERFACE 0x0A +#define USB_SET_INTERFACE 0x0B +#define USB_SYNCH_FRAME 0x0C +#endif + +#define DEF_STRING_DESC_LANG 0x00 +#define DEF_STRING_DESC_MANU 0x01 +#define DEF_STRING_DESC_PROD 0x02 +#define DEF_STRING_DESC_SERN 0x03 + +/* USB hub class request code */ +#ifndef HUB_GET_DESCRIPTOR +#define HUB_GET_STATUS 0x00 +#define HUB_CLEAR_FEATURE 0x01 +#define HUB_GET_STATE 0x02 +#define HUB_SET_FEATURE 0x03 +#define HUB_GET_DESCRIPTOR 0x06 +#define HUB_SET_DESCRIPTOR 0x07 +#endif + +/* USB HID class request code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* Bit Define for USB Request Type */ +#ifndef USB_REQ_TYP_MASK +#define USB_REQ_TYP_IN 0x80 +#define USB_REQ_TYP_OUT 0x00 +#define USB_REQ_TYP_READ 0x80 +#define USB_REQ_TYP_WRITE 0x00 +#define USB_REQ_TYP_MASK 0x60 +#define USB_REQ_TYP_STANDARD 0x00 +#define USB_REQ_TYP_CLASS 0x20 +#define USB_REQ_TYP_VENDOR 0x40 +#define USB_REQ_TYP_RESERVED 0x60 +#define USB_REQ_RECIP_MASK 0x1F +#define USB_REQ_RECIP_DEVICE 0x00 +#define USB_REQ_RECIP_INTERF 0x01 +#define USB_REQ_RECIP_ENDP 0x02 +#define USB_REQ_RECIP_OTHER 0x03 +#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 +#define USB_REQ_FEAT_ENDP_HALT 0x00 +#endif + +/* USB Descriptor Type */ +#ifndef USB_DESCR_TYP_DEVICE +#define USB_DESCR_TYP_DEVICE 0x01 +#define USB_DESCR_TYP_CONFIG 0x02 +#define USB_DESCR_TYP_STRING 0x03 +#define USB_DESCR_TYP_INTERF 0x04 +#define USB_DESCR_TYP_ENDP 0x05 +#define USB_DESCR_TYP_QUALIF 0x06 +#define USB_DESCR_TYP_SPEED 0x07 +#define USB_DESCR_TYP_OTG 0x09 +#define USB_DESCR_TYP_BOS 0X0F +#define USB_DESCR_TYP_HID 0x21 +#define USB_DESCR_TYP_REPORT 0x22 +#define USB_DESCR_TYP_PHYSIC 0x23 +#define USB_DESCR_TYP_CS_INTF 0x24 +#define USB_DESCR_TYP_CS_ENDP 0x25 +#define USB_DESCR_TYP_HUB 0x29 +#endif + +/* USB Device Class */ +#ifndef USB_DEV_CLASS_HUB +#define USB_DEV_CLASS_RESERVED 0x00 +#define USB_DEV_CLASS_AUDIO 0x01 +#define USB_DEV_CLASS_COMMUNIC 0x02 +#define USB_DEV_CLASS_HID 0x03 +#define USB_DEV_CLASS_MONITOR 0x04 +#define USB_DEV_CLASS_PHYSIC_IF 0x05 +#define USB_DEV_CLASS_POWER 0x06 +#define USB_DEV_CLASS_PRINTER 0x07 +#define USB_DEV_CLASS_STORAGE 0x08 +#define USB_DEV_CLASS_HUB 0x09 +#define USB_DEV_CLASS_VEN_SPEC 0xFF +#endif + +/* USB Hub Class Request */ +#ifndef HUB_GET_HUB_DESCRIPTOR +#define HUB_CLEAR_HUB_FEATURE 0x20 +#define HUB_CLEAR_PORT_FEATURE 0x23 +#define HUB_GET_BUS_STATE 0xA3 +#define HUB_GET_HUB_DESCRIPTOR 0xA0 +#define HUB_GET_HUB_STATUS 0xA0 +#define HUB_GET_PORT_STATUS 0xA3 +#define HUB_SET_HUB_DESCRIPTOR 0x20 +#define HUB_SET_HUB_FEATURE 0x20 +#define HUB_SET_PORT_FEATURE 0x23 +#endif + +/* Hub Class Feature Selectors */ +#ifndef HUB_PORT_RESET +#define HUB_C_HUB_LOCAL_POWER 0 +#define HUB_C_HUB_OVER_CURRENT 1 +#define HUB_PORT_CONNECTION 0 +#define HUB_PORT_ENABLE 1 +#define HUB_PORT_SUSPEND 2 +#define HUB_PORT_OVER_CURRENT 3 +#define HUB_PORT_RESET 4 +#define HUB_PORT_POWER 8 +#define HUB_PORT_LOW_SPEED 9 +#define HUB_C_PORT_CONNECTION 16 +#define HUB_C_PORT_ENABLE 17 +#define HUB_C_PORT_SUSPEND 18 +#define HUB_C_PORT_OVER_CURRENT 19 +#define HUB_C_PORT_RESET 20 +#endif + +/* USB HID Class Request Code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* USB UDisk */ +#ifndef USB_BO_CBW_SIZE +#define USB_BO_CBW_SIZE 0x1F +#define USB_BO_CSW_SIZE 0x0D +#endif +#ifndef USB_BO_CBW_SIG0 +#define USB_BO_CBW_SIG0 0x55 +#define USB_BO_CBW_SIG1 0x53 +#define USB_BO_CBW_SIG2 0x42 +#define USB_BO_CBW_SIG3 0x43 +#define USB_BO_CSW_SIG0 0x55 +#define USB_BO_CSW_SIG1 0x53 +#define USB_BO_CSW_SIG2 0x42 +#define USB_BO_CSW_SIG3 0x53 +#endif + +/* USB CDC Class request code */ +#ifndef CDC_GET_LINE_CODING +#define CDC_GET_LINE_CODING 0X21 /* This request allows the host to find out the currently configured line coding */ +#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ +#define CDC_SET_LINE_CTLSTE 0X22 /* This request generates RS-232/V.24 style control signals */ +#define CDC_SEND_BREAK 0X23 /* Sends special carrier modulation used to specify RS-232 style break */ +#endif +/*******************************************************************************/ +/* USBFS Related Register Macro Definition */ + +/* R8_USB_CTRL */ +#define USBFS_UC_HOST_MODE 0x80 +#define USBFS_UC_LOW_SPEED 0x40 +#define USBFS_UC_DEV_PU_EN 0x20 +#define USBFS_UC_SYS_CTRL_MASK 0x30 +#define USBFS_UC_SYS_CTRL0 0x00 +#define USBFS_UC_SYS_CTRL1 0x10 +#define USBFS_UC_SYS_CTRL2 0x20 +#define USBFS_UC_SYS_CTRL3 0x30 +#define USBFS_UC_INT_BUSY 0x08 +#define USBFS_UC_RESET_SIE 0x04 +#define USBFS_UC_CLR_ALL 0x02 +#define USBFS_UC_DMA_EN 0x01 + +/* R8_USB_INT_EN */ +#define USBFS_UIE_DEV_SOF 0x80 +#define USBFS_UIE_DEV_NAK 0x40 +#define USBFS_UID_1_WIRE 0x20 +#define USBFS_UIE_FIFO_OV 0x10 +#define USBFS_UIE_HST_SOF 0x08 +#define USBFS_UIE_SUSPEND 0x04 +#define USBFS_UIE_TRANSFER 0x02 +#define USBFS_UIE_DETECT 0x01 +#define USBFS_UIE_BUS_RST 0x01 + +/* R8_USB_DEV_AD */ +#define USBFS_UDA_GP_BIT 0x80 +#define USBFS_USB_ADDR_MASK 0x7F + +/* R8_USB_MIS_ST */ +#define USBFS_UMS_SOF_PRES 0x80 +#define USBFS_UMS_SOF_ACT 0x40 +#define USBFS_UMS_SIE_FREE 0x20 +#define USBFS_UMS_R_FIFO_RDY 0x10 +#define USBFS_UMS_BUS_RESET 0x08 +#define USBFS_UMS_SUSPEND 0x04 +#define USBFS_UMS_DM_LEVEL 0x02 +#define USBFS_UMS_DEV_ATTACH 0x01 + +/* R8_USB_INT_FG */ +#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode +#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +/* R8_USB_INT_ST */ +#define USBFS_SETUP_ACT 0x80 // RO, indicate current USB transfer SETUP is complete +#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode +#define USBFS_UIS_TOKEN_OUT 0x00 +#define USBFS_UIS_TOKEN_SOF 0x10 +#define USBFS_UIS_TOKEN_IN 0x20 +#define USBFS_UIS_TOKEN_SETUP 0x30 +// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 01: SOF token PID received +// 10: IN token PID received +// 11: SETUP token PID received +#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +#define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received + +/* R8_UDEV_CTRL */ +#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define USBFS_UD_GP_BIT 0x02 // general purpose bit +#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +/* R8_UEP4_1_MOD */ +#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA +// 0 0 x: disable endpoint and disable buffer +// 1 0 0: 64 bytes buffer for receiving (OUT endpoint) +// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes +// 0 1 0: 64 bytes buffer for transmittal (IN endpoint) +// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes +// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes +// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes +#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA +// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes +// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes +// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes + +/* R8_UEP2_3_MOD */ +#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +/* R8_UEP567_MOD */ + +#define USBFS_UEP5_RX_EN 0x02 // enable USB endpoint 5 receiving (OUT) +#define USBFS_UEP5_TX_EN 0x01 // enable USB endpoint 5 transmittal (IN) +#define USBFS_UEP6_RX_EN 0x08 // enable USB endpoint 6 receiving (OUT) +#define USBFS_UEP6_TX_EN 0x04 // enable USB endpoint 6 transmittal (IN) +#define USBFS_UEP7_RX_EN 0x20 // enable USB endpoint 7 receiving (OUT) +#define USBFS_UEP7_TX_EN 0x10 // enable USB endpoint 7 transmittal (IN) + +/* R8_UEPn_TX_CTRL */ +#define USBFS_UEP_T_AUTO_TOG (1<<4) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_T_TOG (1<<6) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define USBFS_UEP_T_RES_MASK (3<<0) // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES_ACK (0<<1) +#define USBFS_UEP_T_RES_NONE (1<<0) +#define USBFS_UEP_T_RES_NAK (1<<1) +#define USBFS_UEP_T_RES_STALL (3<<0) +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +// host aux setup + +/* R8_UEPn_RX_CTRL, n=0-7 */ +#define USBFS_UEP_R_AUTO_TOG (1<<4) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_R_TOG (1<<7) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBFS_UEP_R_RES_MASK (3<<2) // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES_ACK (0<<3) +#define USBFS_UEP_R_RES_NONE (1<<2) +#define USBFS_UEP_R_RES_NAK (1<<3) +#define USBFS_UEP_R_RES_STALL (3<<2) +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) + +/* R8_UHOST_CTRL */ +#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +/* R32_UH_EP_MOD */ +#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for transmittal (OUT endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes +#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint +// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for receiving (IN endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes + +/* R8_UH_SETUP */ +#define USBFS_UH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub +#define USBFS_UH_SOF_EN 0x40 // USB host automatic SOF enable + +/* R8_UH_EP_PID */ +#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer +#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer + + /* R8_UH_RX_CTRL */ + #define USBFS_UH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle + #define USBFS_UH_R_TOG (1<<7) // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 + #define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + + /* R8_UH_TX_CTRL */ + #define USBFS_UH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle + #define USBFS_UH_T_TOG (1<<6) // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 + #define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + + +/*******************************************************************************/ +/* Struct Definition */ + +/* USB Setup Request */ +typedef struct __attribute__((packed)) _USB_SETUP_REQ +{ + uint8_t bRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} USB_SETUP_REQ, *PUSB_SETUP_REQ; + +/* USB Device Descriptor */ +typedef struct __attribute__((packed)) _USB_DEVICE_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint16_t idVendor; + uint16_t idProduct; + uint16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} USB_DEV_DESCR, *PUSB_DEV_DESCR; + +/* USB Configuration Descriptor */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t MaxPower; +} USB_CFG_DESCR, *PUSB_CFG_DESCR; + +/* USB Interface Descriptor */ +typedef struct __attribute__((packed)) _USB_INTERF_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} USB_ITF_DESCR, *PUSB_ITF_DESCR; + +/* USB Endpoint Descriptor */ +typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint8_t wMaxPacketSizeL; + uint8_t wMaxPacketSizeH; + uint8_t bInterval; +} USB_ENDP_DESCR, *PUSB_ENDP_DESCR; + +/* USB Configuration Descriptor Set */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG +{ + USB_CFG_DESCR cfg_descr; + USB_ITF_DESCR itf_descr; + USB_ENDP_DESCR endp_descr[ 1 ]; +} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG; + +/* USB HUB Descriptor */ +typedef struct __attribute__((packed)) _USB_HUB_DESCR +{ + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint8_t wHubCharacteristicsL; + uint8_t wHubCharacteristicsH; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable; + uint8_t PortPwrCtrlMask; +} USB_HUB_DESCR, *PUSB_HUB_DESCR; + +/* USB HID Descriptor */ +typedef struct __attribute__((packed)) _USB_HID_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdHID; + uint8_t bCountryCode; + uint8_t bNumDescriptors; + uint8_t bDescriptorTypeX; + uint8_t wDescriptorLengthL; + uint8_t wDescriptorLengthH; +} USB_HID_DESCR, *PUSB_HID_DESCR; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CBW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCBW_DataLen; + uint8_t mCBW_Flag; + uint8_t mCBW_LUN; + uint8_t mCBW_CB_Len; + uint8_t mCBW_CB_Buf[ 16 ]; +} UDISK_BOC_CBW, *PXUDISK_BOC_CBW; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CSW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCSW_Residue; + uint8_t mCSW_Status; +} UDISK_BOC_CSW, *PXUDISK_BOC_CSW; + + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32X035_USB_H */ diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_usbpd.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_usbpd.h new file mode 100644 index 00000000..7ca10083 --- /dev/null +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_usbpd.h @@ -0,0 +1,412 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_usbpd.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the USBPD + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_USBPD_H +#define __CH32X035_USBPD_H + + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32x035.h" + +#ifndef VOID +#define VOID void +#endif +#ifndef CONST +#define CONST const +#endif +#ifndef BOOL +typedef unsigned char BOOL; +#endif +#ifndef BOOLEAN +typedef unsigned char BOOLEAN; +#endif +#ifndef CHAR +typedef char CHAR; +#endif +#ifndef INT8 +typedef char INT8; +#endif +#ifndef INT16 +typedef short INT16; +#endif +#ifndef INT32 +typedef long INT32; +#endif +#ifndef UINT8 +typedef unsigned char UINT8; +#endif +#ifndef UINT16 +typedef unsigned short UINT16; +#endif +#ifndef UINT32 +typedef unsigned long UINT32; +#endif +#ifndef UINT8V +typedef unsigned char volatile UINT8V; +#endif +#ifndef UINT16V +typedef unsigned short volatile UINT16V; +#endif +#ifndef UINT32V +typedef unsigned long volatile UINT32V; +#endif + +#ifndef PVOID +typedef void *PVOID; +#endif +#ifndef PCHAR +typedef char *PCHAR; +#endif +#ifndef PCHAR +typedef const char *PCCHAR; +#endif +#ifndef PINT8 +typedef char *PINT8; +#endif +#ifndef PINT16 +typedef short *PINT16; +#endif +#ifndef PINT32 +typedef long *PINT32; +#endif +#ifndef PUINT8 +typedef unsigned char *PUINT8; +#endif +#ifndef PUINT16 +typedef unsigned short *PUINT16; +#endif +#ifndef PUINT32 +typedef unsigned long *PUINT32; +#endif +#ifndef PUINT8V +typedef volatile unsigned char *PUINT8V; +#endif +#ifndef PUINT16V +typedef volatile unsigned short *PUINT16V; +#endif +#ifndef PUINT32V +typedef volatile unsigned long *PUINT32V; +#endif + + /******************************************************************************/ +/* Related macro definitions */ + +/* Define the return value of the function */ +#ifndef SUCCESS +#define SUCCESS 0 +#endif +#ifndef FAIL +#define FAIL 0xFF +#endif + +/* Register Bit Definition */ +/* USBPD->CONFIG */ +#define PD_FILT_ED (1<<0) /* PD pin input filter enable */ +#define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */ +#define CC_SEL (1<<2) /* Select PD communication port */ +#define PD_DMA_EN (1<<3) /* Enable DMA for USBPD */ +#define PD_RST_EN (1<<4) /* PD mode reset command enable */ +#define WAKE_POLAR (1<<5) /* PD port wake-up level */ +#define IE_PD_IO (1<<10) /* PD IO interrupt enable */ +#define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */ +#define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */ +#define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */ +#define IE_RX_RESET (1<<14) /* Reset interrupt enable */ +#define IE_TX_END (1<<15) /* Transfer completion interrupt enable */ + +/* USBPD->CONTROL */ +#define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */ +#define BMC_START (1<<1) /* BMC send start signal */ +#define RX_STATE_0 (1<<2) /* PD received state bit 0 */ +#define RX_STATE_1 (1<<3) /* PD received state bit 1 */ +#define RX_STATE_2 (1<<4) /* PD received state bit 2 */ +#define DATA_FLAG (1<<5) /* Cache data valid flag bit */ +#define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */ +#define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */ + +/* USBPD->TX_SEL */ +#define TX_SEL1 (0<<0) +#define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */ +#define TX_SEL1_RST1 (1<<0) /* 1-RST1 */ +#define TX_SEL2_Mask (3<<2) +#define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */ +#define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */ +#define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */ +#define TX_SEL3_Mask (3<<4) +#define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */ +#define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */ +#define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */ +#define TX_SEL4_Mask (3<<6) +#define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */ +#define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */ +#define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */ + +/* USBPD->STATUS */ +#define BMC_AUX_Mask (3<<0) /* Clear BMC auxiliary information */ +#define BMC_AUX_INVALID (0<<0) /* 00-Invalid */ +#define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */ +#define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */ +#define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */ +#define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */ +#define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */ +#define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */ +#define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */ +#define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */ +#define IF_TX_END (1<<7) /* Transfer completion interrupt flag */ + +/* USBPD->PORT_CC1 */ +/* USBPD->PORT_CC2 */ +#define PA_CC_AI (1<<0) /* CC port comparator analogue input */ +#define CC_PD (1<<1) /* CC port pull-down resistor enable */ +#define CC_PU_Mask (3<<2) /* Clear CC port pull-up current */ +#define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */ +#define CC_PU_330 (1<<2) /* 01-330uA */ +#define CC_PU_180 (2<<2) /* 10-180uA */ +#define CC_PU_80 (3<<2) /* 11-80uA */ +#define CC_LVE (1<<4) /* CC port output low voltage enable */ +#define CC_CMP_Mask (7<<5) /* Clear CC_CMP*/ +#define CC_NO_CMP (0<<5) /* 000-closed */ +#define CC_CMP_22 (2<<5) /* 010-0.22V */ +#define CC_CMP_45 (3<<5) /* 011-0.45V */ +#define CC_CMP_55 (4<<5) /* 100-0.55V */ +#define CC_CMP_66 (5<<5) /* 101-0.66V */ +#define CC_CMP_95 (6<<5) /* 110-0.95V */ +#define CC_CMP_123 (7<<5) /* 111-1.23V */ +#define USBPD_IN_HVT (1<<9) +/********************************************************* + * PD pin PC14/PC15 high threshold input mode: + * 1-High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication + * 0-Normal GPIO threshold input + * *******************************************************/ +#define USBPD_PHY_V33 (1<<8) +/********************************************************** +* PD transceiver PHY pull-up limit configuration bits: +* 1-Direct use of VDD for GPIO applications or PD applications with VDD voltage of 3.3V +* 0-LDO buck enabled, limited to approx 3.3V, for PD applications with VDD more than 4V +* ********************************************************/ + +/* Control Message Types */ +#define DEF_TYPE_RESERVED 0x00 +#define DEF_TYPE_GOODCRC 0x01 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GOTOMIN 0x02 /* Send By: Source */ +#define DEF_TYPE_ACCEPT 0x03 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_REJECT 0x04 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_PING 0x05 /* Send By: Source */ +#define DEF_TYPE_PS_RDY 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SRC_CAP 0x07 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_SNK_CAP 0x08 /* Send By: Source,DRP */ +#define DEF_TYPE_DR_SWAP 0x09 /* Send By: Source,Sink */ +#define DEF_TYPE_PR_SWAP 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_VCONN_SWAP 0x0B /* Send By: Source,Sink */ +#define DEF_TYPE_WAIT 0x0C /* Send By: Source,Sink */ +#define DEF_TYPE_SOFT_RESET 0x0D /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET 0x0E /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET_CMP 0x0F /* Send By: Source,Sink */ +#define DEF_TYPE_NOT_SUPPORT 0x10 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GET_SRC_CAP_EX 0x11 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_STATUS 0x12 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_STATUS_R 0X02 /* ext=1 */ +#define DEF_TYPE_FR_SWAP 0x13 /* Send By: Sink */ +#define DEF_TYPE_GET_PPS_STATUS 0x14 /* Send By: Sink */ +#define DEF_TYPE_GET_CTY_CODES 0x15 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SNK_CAP_EX 0x16 /* Send By: Source,DRP */ +#define DEF_TYPE_GET_SRC_INFO 0x17 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_REVISION 0x18 /* Send By: Source,Sink */ + +/* Data Message Types */ +#define DEF_TYPE_SRC_CAP 0x01 /* Send By: Source,Dual-Role Power */ +#define DEF_TYPE_REQUEST 0x02 /* Send By: Sink */ +#define DEF_TYPE_BIST 0x03 /* Send By: Tester,Source,Sink */ +#define DEF_TYPE_SNK_CAP 0x04 /* Send By: Sink,Dual-Role Power */ +#define DEF_TYPE_BAT_STATUS 0x05 /* Send By: Source,Sink */ +#define DEF_TYPE_ALERT 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_CTY_INFO 0x07 /* Send By: Source,Sink */ +#define DEF_TYPE_ENTER_USB 0x08 /* Send By: DFP */ +#define DEF_TYPE_EPR_REQUEST 0x09 /* Send By: Sink */ +#define DEF_TYPE_EPR_MODE 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_SRC_INFO 0x0B /* Send By: Source */ +#define DEF_TYPE_REVISION 0x0C /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_VENDOR_DEFINED 0x0F /* Send By: Source,Sink,Cable Plug */ + +/* Vendor Define Message Command */ +#define DEF_VDM_DISC_IDENT 0x01 +#define DEF_VDM_DISC_SVID 0x02 +#define DEF_VDM_DISC_MODE 0x03 +#define DEF_VDM_ENTER_MODE 0x04 +#define DEF_VDM_EXIT_MODE 0x05 +#define DEF_VDM_ATTENTION 0x06 +#define DEF_VDM_DP_S_UPDATE 0x10 +#define DEF_VDM_DP_CONFIG 0x11 + +/* PD Revision */ +#define DEF_PD_REVISION_10 0x00 +#define DEF_PD_REVISION_20 0x01 +#define DEF_PD_REVISION_30 0x02 + + +/* PD PHY Channel */ +#define DEF_PD_CC1 0x00 +#define DEF_PD_CC2 0x01 + +#define PIN_CC1 GPIO_Pin_14 +#define PIN_CC2 GPIO_Pin_15 + +/* PD Tx Status */ +#define DEF_PD_TX_OK 0x00 +#define DEF_PD_TX_FAIL 0x01 + +/* PDO INDEX */ +#define PDO_INDEX_1 1 +#define PDO_INDEX_2 2 +#define PDO_INDEX_3 3 +#define PDO_INDEX_4 4 +#define PDO_INDEX_5 5 + +/******************************************************************************/ + +#define UPD_TMR_TX_48M (80-1) /* timer value for USB PD BMC transmittal @Fsys=48MHz */ +#define UPD_TMR_RX_48M (120-1) /* timer value for USB PD BMC receiving @Fsys=48MHz */ +#define UPD_TMR_TX_24M (40-1) /* timer value for USB PD BMC transmittal @Fsys=24MHz */ +#define UPD_TMR_RX_24M (60-1) /* timer value for USB PD BMC receiving @Fsys=24MHz */ +#define UPD_TMR_TX_12M (20-1) /* timer value for USB PD BMC transmittal @Fsys=12MHz */ +#define UPD_TMR_RX_12M (30-1) /* timer value for USB PD BMC receiving @Fsys=12MHz */ + +#define MASK_PD_STAT 0x03 /* Bit mask for current PD status */ +#define PD_RX_SOP0 0x01 /* SOP0 received */ +#define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */ +#define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */ + +#define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */ +#define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */ +#define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */ +#define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/ +#define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/ + + +#define bCC_CMP_22 0X01 +#define bCC_CMP_45 0X02 +#define bCC_CMP_55 0X04 +#define bCC_CMP_66 0X08 +#define bCC_CMP_95 0X10 +#define bCC_CMP_123 0X20 +#define bCC_CMP_220 0X40 + +/******************************************************************************/ +/* PD State Machine */ +typedef enum +{ + STA_IDLE = 0, /* 0: No task status */ + STA_DISCONNECT, /* 1: Disconnection */ + STA_SRC_CONNECT, /* 2: SRC connect */ + STA_RX_SRC_CAP_WAIT, /* 3: Waiting to receive SRC_CAP */ + STA_RX_SRC_CAP, /* 4: SRC_CAP received */ + STA_TX_REQ, /* 5: Send REQUEST */ + STA_RX_ACCEPT_WAIT, /* 6: Waiting to receive ACCEPT */ + STA_RX_ACCEPT, /* 7: ACCEPT received */ + STA_RX_REJECT, /* 8: REJECT received */ + STA_RX_PS_RDY_WAIT, /* 9: Waiting to receive PS_RDY */ + STA_RX_PS_RDY, /* 10: PS_RDY received */ + STA_SINK_CONNECT, /* 11: SNK access */ + STA_TX_SRC_CAP, /* 12: Send SRC_CAP */ + STA_RX_REQ_WAIT, /* 13: Waiting to receive REQUEST */ + STA_RX_REQ, /* 14: REQUEST received */ + STA_TX_ACCEPT, /* 15: Send ACCEPT */ + STA_TX_REJECT, /* 16: Send REJECT */ + STA_ADJ_VOL, /* 17: Adjustment of output voltage and current */ + STA_TX_PS_RDY, /* 18: Send PS_RDY */ + STA_TX_DR_SWAP, /* 19: Send DR_SWAP */ + STA_RX_DR_SWAP_ACCEPT, /* 20: Waiting to receive the answer ACCEPT from DR_SWAP */ + STA_TX_PR_SWAP, /* 21: Send PR_SWAP */ + STA_RX_PR_SWAP_ACCEPT, /* 22: Waiting to receive the answer ACCEPT from PR_SWAP */ + STA_RX_PR_SWAP_PS_RDY, /* 23: Waiting to receive the answer PS_RDY from PR_SWAP */ + STA_TX_PR_SWAP_PS_RDY, /* 24: Send answer PS_RDY for PR_SWAP */ + STA_PR_SWAP_RECON_WAIT, /* 25: Wait for PR_SWAP before reconnecting */ + STA_SRC_RECON_WAIT, /* 26: Waiting for SRC to reconnect */ + STA_SINK_RECON_WAIT, /* 27: Waiting for SNK to reconnect */ + STA_RX_APD_PS_RDY_WAIT, /* 28: Waiting for PS_RDY from the receiving adapter */ + STA_RX_APD_PS_RDY, /* 29: PS_RDY received from the adapter */ + STA_MODE_SWITCH, /* 30: Mode switching */ + STA_TX_SOFTRST, /* 31: Sending a software reset */ + STA_TX_HRST, /* 32: Send hardware reset */ + STA_PHY_RST, /* 33: PHY reset */ + STA_APD_IDLE_WAIT, /* 34: Waiting for the adapter to become idle */ +} CC_STATUS; + +/******************************************************************************/ +/* PD Message Header Struct */ +typedef union +{ + struct _Message_Header + { + UINT8 MsgType: 5; /* Message Type */ + UINT8 PDRole: 1; /* 0-UFP; 1-DFP */ + UINT8 SpecRev: 2; /* 00-Rev1.0; 01-Rev2.0; 10-Rev3.0; */ + UINT8 PRRole: 1; /* 0-Sink; 1-Source */ + UINT8 MsgID: 3; + UINT8 NumDO: 3; + UINT8 Ext: 1; + }Message_Header; + UINT16 Data; +}_Message_Header; + +/******************************************************************************/ +/* Bit definition */ +typedef union +{ + struct _BITS_ + { + UINT8 Msg_Recvd: 1; /* Notify the main program of the receipt of a PD packet */ + UINT8 Connected: 1; /* PD Physical Layer Connected Flag */ + UINT8 Stop_Det_Chk: 1; /* 0-Enable detection; 1-Disable disconnection detection */ + UINT8 PD_Role: 1; /* 0-UFP; 1-DFP */ + UINT8 PR_Role: 1; /* 0-Sink; 1-Source */ + UINT8 Auto_Ack_PRRole: 1; /* Role used by auto-responder 0:SINK; 1:SOURCE */ + UINT8 PD_Version: 1; /* PD version 0-PD2.0; 1-PD3.0 */ + UINT8 VDM_Version: 1; /* VDM Version 0-1.0 1-2.0 */ + UINT8 HPD_Connected: 1; /* HPD Physical Layer Connected Flag */ + UINT8 HPD_Det_Chk: 1; /* 0-turn off HPD connection detection; 1-turn on HPD connection detection */ + UINT8 CC_Sel_En: 1; /* 0-CC channel selection toggle enable; 1-CC channel selection toggle disable */ + UINT8 CC_Sel_State: 1; /* 0-CC channel selection switches to 0; 1-CC channel selection switches to 1 */ + UINT8 PD_Comm_Succ: 1; /* 0-PD communication unsuccessful; 1-PD communication successful; */ + UINT8 Recv: 3; + }Bit; + UINT16 Bit_Flag; +}_BIT_FLAG; + +/* PD control-related structures */ +typedef struct _PD_CONTROL +{ + CC_STATUS PD_State; /* PD communication status machine */ + CC_STATUS PD_State_Last; /* PD communication status machine (last value) */ + UINT8 Msg_ID; /* ID of the message sent */ + UINT8 Det_Timer; /* PD connection status detection timing */ + UINT8 Det_Cnt; /* Number of PD connection status detections */ + UINT8 Det_Sel_Cnt; /* Number of SEL toggles for PD connection status detection */ + UINT8 HPD_Det_Timer; /* HPD connection detection timing */ + UINT8 HPD_Det_Cnt; /* HPD pin connection status detection count */ + UINT16 PD_Comm_Timer; /* PD shared timing variables */ + UINT8 ReqPDO_Idx; /* Index of the requested PDO, valid values 1-7 */ + UINT16 PD_BusIdle_Timer; /* Bus Idle Time Timer */ + UINT8 Mode_Try_Cnt; /* Number of retries for current mode, highest bit marks mode */ + UINT8 Err_Op_Cnt; /* Exception operation count */ + UINT8 Adapter_Idle_Cnt; /* Adapter communication idle timing */ + _BIT_FLAG Flag; /* Flag byte bit definition */ +}PD_CONTROL, *pPD_CONTROL; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_dbgmcu.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_dbgmcu.c index c7adf678..2bebff9c 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_dbgmcu.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_dbgmcu.c @@ -112,6 +112,7 @@ void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) * CH32X035G8U6-0x035606x1 * CH32X035G8R6-0x035B06x1 * CH32X035F7P6-0x035706x1 + * CH32X033F8P6-0x035A06x1 */ uint32_t DBGMCU_GetCHIPID( void ) { diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_flash.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_flash.c index 937513d8..a1effe72 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_flash.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_flash.c @@ -2,7 +2,7 @@ * File Name : ch32x035_flash.c * Author : WCH * Version : V1.0.0 - * Date : 2023/04/06 + * Date : 2023/12/26 * Description : This file provides all the FLASH firmware functions. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -12,7 +12,7 @@ #include "ch32x035_flash.h" /* Flash Access Control Register bits */ -#define ACR_LATENCY_Mask ((uint32_t)0x00000038) +#define ACR_LATENCY_Mask ((uint32_t)0xFFFFFFFC) /* Flash Control Register bits */ #define CR_PER_Set ((uint32_t)0x00000002) @@ -28,6 +28,7 @@ #define CR_FLOCK_Set ((uint32_t)0x00008000) #define CR_PAGE_PG ((uint32_t)0x00010000) #define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_PAGE_ER_Reset ((uint32_t)0xFFFDFFFF) #define CR_BUF_LOAD ((uint32_t)0x00040000) #define CR_BUF_RST ((uint32_t)0x00080000) #define CR_BER32 ((uint32_t)0x00800000) @@ -56,6 +57,15 @@ #define EraseTimeout ((uint32_t)0x000B0000) #define ProgramTimeout ((uint32_t)0x00005000) +/* Flash Program Valid Address */ +#define ValidAddrStart (FLASH_BASE) +#define ValidAddrEnd (FLASH_BASE + 0xF800) + +/* FLASH Size */ +#define Size_256B 0x100 +#define Size_1KB 0x400 +#define Size_32KB 0x8000 + /******************************************************************************** * @fn FLASH_SetLatency * @@ -122,6 +132,7 @@ FLASH_Status FLASH_ErasePage(uint32_t Page_Address) if(status == FLASH_COMPLETE) { + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); FLASH->CTLR |= CR_PER_Set; FLASH->ADDR = Page_Address; FLASH->CTLR |= CR_STRT_Set; @@ -149,6 +160,7 @@ FLASH_Status FLASH_EraseAllPages(void) status = FLASH_WaitForLastOperation(EraseTimeout); if(status == FLASH_COMPLETE) { + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); FLASH->CTLR |= CR_MER_Set; FLASH->CTLR |= CR_STRT_Set; @@ -180,6 +192,7 @@ FLASH_Status FLASH_EraseOptionBytes(void) FLASH->OBKEYR = FLASH_KEY1; FLASH->OBKEYR = FLASH_KEY2; + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); FLASH->CTLR |= CR_OPTER_Set; FLASH->CTLR |= CR_STRT_Set; status = FLASH_WaitForLastOperation(EraseTimeout); @@ -631,6 +644,8 @@ void FLASH_Lock_Fast(void) */ void FLASH_BufReset(void) { + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + FLASH->CTLR |= CR_PAGE_PG; FLASH->CTLR |= CR_BUF_RST; while(FLASH->STATR & SR_BSY) @@ -650,6 +665,8 @@ void FLASH_BufReset(void) */ void FLASH_BufLoad(uint32_t Address, uint32_t Data0) { + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + FLASH->CTLR |= CR_PAGE_PG; *(__IO uint32_t *)(Address) = Data0; FLASH->CTLR |= CR_BUF_LOAD; @@ -669,6 +686,8 @@ void FLASH_BufLoad(uint32_t Address, uint32_t Data0) */ void FLASH_ErasePage_Fast(uint32_t Page_Address) { + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + FLASH->CTLR |= CR_PAGE_ER; FLASH->ADDR = Page_Address; FLASH->CTLR |= CR_STRT_Set; @@ -688,6 +707,8 @@ void FLASH_ErasePage_Fast(uint32_t Page_Address) */ void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address) { + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + Block_Address &= 0xFFFF8000; FLASH->CTLR |= CR_BER32; @@ -709,6 +730,8 @@ void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address) */ void FLASH_ProgramPage_Fast(uint32_t Page_Address) { + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + FLASH->CTLR |= CR_PAGE_PG; FLASH->ADDR = Page_Address; FLASH->CTLR |= CR_STRT_Set; @@ -741,3 +764,277 @@ void SystemReset_StartMode(uint32_t Mode) FLASH_Lock(); } + +/********************************************************************* + * @fn ROM_ERASE + * + * @brief Select erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). + * Cnt - Erases count. + * Erase_Size - Erases size select.The returned value can be: + * Size_32KB, Size_1KB, Size_256B. + * + * @return none. + */ +static void ROM_ERASE(uint32_t StartAddr, uint32_t Cnt, uint32_t Erase_Size) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + do{ + if(Erase_Size == Size_32KB) + { + FLASH->CTLR |= CR_BER32; + } + else if(Erase_Size == Size_1KB) + { + FLASH->CTLR |= CR_PER_Set; + } + else if(Erase_Size == Size_256B) + { + FLASH->CTLR |= CR_PAGE_ER; + } + + FLASH->ADDR = StartAddr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + + if(Erase_Size == Size_32KB) + { + FLASH->CTLR &= ~CR_BER32; + StartAddr += Size_32KB; + } + else if(Erase_Size == Size_1KB) + { + FLASH->CTLR &= ~CR_PER_Set; + StartAddr += Size_1KB; + } + else if(Erase_Size == Size_256B) + { + FLASH->CTLR &= ~CR_PAGE_ER; + StartAddr += Size_256B; + } + }while(--Cnt); +} + +/********************************************************************* + * @fn FLASH_ROM_ERASE + * + * @brief Erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). + * Length - Erases Flash start Length(Length%256 == 0). + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length) +{ + uint32_t Addr0 = 0, Addr1 = 0, Length0 = 0, Length1 = 0; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + Addr0 = StartAddr; + + if(Length >= Size_32KB) + { + Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_1KB) + { + Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_256B) + { + Length0 = Length; + } + + /* Erase 32KB */ + if(Length0 >= Size_32KB)//front + { + Length = Length0; + if(Addr0 & (Size_32KB - 1)) + { + Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 15), Size_32KB); + } + + if(Length1 >= Size_32KB)//back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_32KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_32KB - 1))); + Length1 = (StartAddr + Length1) & (Size_32KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 15), Size_32KB); + } + + /* Erase 1KB */ + if(Length0 >= Size_1KB) //front + { + Length = Length0; + if(Addr0 & (Size_1KB - 1)) + { + Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 10), Size_1KB); + } + + if(Length1 >= Size_1KB) //back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_1KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_1KB - 1))); + Length1 = (StartAddr + Length1) & (Size_1KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 10), Size_1KB); + } + + /* Erase 256B */ + if(Length0)//front + { + ROM_ERASE(Addr0, (Length0 >> 8), Size_256B); + } + + if(Length1)//back + { + ROM_ERASE(Addr1, (Length1 >> 8), Size_256B); + } + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} + +/********************************************************************* + * @fn FLASH_ROM_WRITE + * + * @brief Writes a specified FLASH . + * + * @param StartAddr - Writes Flash start address(StartAddr%256 == 0). + * Length - Writes Flash start Length(Length%256 == 0). + * pbuf - Writes Flash value buffer. + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length) +{ + uint32_t i, adr; + uint8_t size; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + adr = StartAddr; + i = Length >> 8; + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + do{ + FLASH->CTLR |= CR_PAGE_PG; + FLASH->CTLR |= CR_BUF_RST; + while(FLASH->STATR & SR_BSY) + ; + size = 64; + while(size) + { + *(uint32_t *)StartAddr = *(uint32_t *)pbuf; + FLASH->CTLR |= CR_BUF_LOAD; + while(FLASH->STATR & SR_BSY) + ; + StartAddr += 4; + pbuf += 1; + size -= 1; + } + + FLASH->ADDR = adr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + adr += 256; + }while(--i); + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_gpio.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_gpio.c index 6aff8f3a..122a9dc6 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_gpio.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_gpio.c @@ -2,7 +2,7 @@ * File Name : ch32x035_gpio.c * Author : WCH * Version : V1.0.0 - * Date : 2023/04/06 + * Date : 2024/08/06 * Description : This file provides all the GPIO firmware functions. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -124,19 +124,25 @@ void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF00)) != 0x00) { - if(GPIOx == GPIOA) + if(((*( uint32_t * )0x1FFFF704) & 0x000000F0) == 0) { - tmpreg = CFGHR_tmpA; - } - else if(GPIOx == GPIOB) - { - tmpreg = CFGHR_tmpB; + if(GPIOx == GPIOA) + { + tmpreg = CFGHR_tmpA; + } + else if(GPIOx == GPIOB) + { + tmpreg = CFGHR_tmpB; + } + else if(GPIOx == GPIOC) + { + tmpreg = CFGHR_tmpC; + } } - else if(GPIOx == GPIOC) + else { - tmpreg = CFGHR_tmpC; + tmpreg = GPIOx->CFGHR; } - for(pinpos = 0x00; pinpos < 0x08; pinpos++) { pos = (((uint32_t)0x01) << (pinpos + 0x08)); @@ -161,18 +167,20 @@ void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) } } GPIOx->CFGHR = tmpreg; - - if(GPIOx == GPIOA) - { - CFGHR_tmpA = tmpreg; - } - else if(GPIOx == GPIOB) + if(((*( uint32_t * )0x1FFFF704) & 0x000000F0) == 0) { - CFGHR_tmpB = tmpreg; - } - else if(GPIOx == GPIOC) - { - CFGHR_tmpC = tmpreg; + if(GPIOx == GPIOA) + { + CFGHR_tmpA = tmpreg; + } + else if(GPIOx == GPIOB) + { + CFGHR_tmpB = tmpreg; + } + else if(GPIOx == GPIOC) + { + CFGHR_tmpC = tmpreg; + } } } @@ -326,15 +334,8 @@ uint32_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) */ void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { - if((GPIO_Pin & ((uint32_t)0x00FFFF)) != 0x00) - { - GPIOx->BSHR = GPIO_Pin; - } - - if(GPIO_Pin > 0x00FFFF) - { - GPIOx->BSXR = (GPIO_Pin>>0x10); - } + GPIOx->BSHR = (GPIO_Pin & (uint32_t)0x0000FFFF); + GPIOx->BSXR = ((GPIO_Pin & (uint32_t)0xFFFF0000) >> 0x10); } /********************************************************************* @@ -370,15 +371,8 @@ void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, BitAction BitVal) { if(BitVal != Bit_RESET) { - if((GPIO_Pin & ((uint32_t)0x00FFFF)) != 0x00) - { - GPIOx->BSHR = GPIO_Pin; - } - - if(GPIO_Pin > 0x00FFFF) - { - GPIOx->BSXR = (GPIO_Pin>>0x10); - } + GPIOx->BSHR = (GPIO_Pin & (uint32_t)0x0000FFFF); + GPIOx->BSXR = ((GPIO_Pin & (uint32_t)0xFFFF0000) >> 0x10); } else { @@ -575,17 +569,177 @@ void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint16_t GPIO_PinSource) void GPIO_IPD_Unused(void) { GPIO_InitTypeDef GPIO_InitStructure = {0}; + uint32_t chip = 0; + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC, ENABLE); + chip = *( uint32_t * )0x1FFFF704 & (~0x000000F1); + switch(chip) + { + case 0x03510600: //CH32X035C8T6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_16|GPIO_Pin_17\ + |GPIO_Pin_18|GPIO_Pin_19\ + |GPIO_Pin_20|GPIO_Pin_21; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x03560600: //CH32X035G8U6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16|GPIO_Pin_15\ + |GPIO_Pin_17|GPIO_Pin_18\ + |GPIO_Pin_19|GPIO_Pin_20\ + |GPIO_Pin_21|GPIO_Pin_22\ + |GPIO_Pin_23|GPIO_Pin_14\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_16|GPIO_Pin_17\ + |GPIO_Pin_18|GPIO_Pin_19\ + |GPIO_Pin_20|GPIO_Pin_21; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x035B0600: //CH32X035G8R6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16|GPIO_Pin_15\ + |GPIO_Pin_17|GPIO_Pin_18\ + |GPIO_Pin_19|GPIO_Pin_20\ + |GPIO_Pin_21|GPIO_Pin_22\ + |GPIO_Pin_23|GPIO_Pin_14\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_16|GPIO_Pin_17\ + |GPIO_Pin_18|GPIO_Pin_19\ + |GPIO_Pin_20|GPIO_Pin_21; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x035E0600: //CH32X035F8U6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16|GPIO_Pin_15\ + |GPIO_Pin_17|GPIO_Pin_18\ + |GPIO_Pin_19|GPIO_Pin_20\ + |GPIO_Pin_21|GPIO_Pin_22|GPIO_Pin_23\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13|GPIO_Pin_14; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_9\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_10\ + |GPIO_Pin_16|GPIO_Pin_15\ + |GPIO_Pin_14|GPIO_Pin_13\ + |GPIO_Pin_17|GPIO_Pin_18\ + |GPIO_Pin_19|GPIO_Pin_20|GPIO_Pin_21; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x03570600: //CH32X035F7P6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_16|GPIO_Pin_17\ + |GPIO_Pin_18|GPIO_Pin_19\ + |GPIO_Pin_20|GPIO_Pin_21\ + |GPIO_Pin_22|GPIO_Pin_23; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7|GPIO_Pin_8\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_16|GPIO_Pin_17\ + |GPIO_Pin_18|GPIO_Pin_19\ + |GPIO_Pin_20|GPIO_Pin_21; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x03117000: //CH32X033F8P6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16|GPIO_Pin_15\ + |GPIO_Pin_17|GPIO_Pin_18\ + |GPIO_Pin_19|GPIO_Pin_20\ + |GPIO_Pin_21|GPIO_Pin_22|GPIO_Pin_23\ + |GPIO_Pin_8|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_16|GPIO_Pin_17\ + |GPIO_Pin_18|GPIO_Pin_19\ + |GPIO_Pin_20|GPIO_Pin_21\ + |GPIO_Pin_22|GPIO_Pin_23; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_20|GPIO_Pin_21\ + |GPIO_Pin_22|GPIO_Pin_23; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + default: + { + break; + } - /* All pull-up */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE); - RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); - GPIO_PinRemapConfig(GPIO_Remap_SWJ_Disable, ENABLE); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_Init(GPIOC, &GPIO_InitStructure); + } } diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_i2c.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_i2c.c index 77e7dbb5..97febb0e 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_i2c.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_i2c.c @@ -2,7 +2,7 @@ * File Name : ch32x035_i2c.c * Author : WCH * Version : V1.0.0 - * Date : 2023/04/06 + * Date : 2024/03/19 * Description : This file provides all the I2C firmware functions. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -870,7 +870,7 @@ FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) * read/write to I2C_DATAR register (I2C_SendData()). * - ADDR (Address sent) is cleared by software sequence: a read operation to * I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to - * I2C_SATR2 register ((void)(I2Cx->SR2)). + * I2C_SATR2 register ((void)(I2Cx->STAR2)). * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1 * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR * register (I2C_SendData()). @@ -951,7 +951,7 @@ ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) * read/write to I2C_DATAR register (I2C_SendData()). * - ADDR (Address sent) is cleared by software sequence: a read operation to * I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to - * I2C_STAR2 register ((void)(I2Cx->SR2)). + * I2C_STAR2 register ((void)(I2Cx->STAR2)). * - SB (Start Bit) is cleared by software sequence: a read operation to * I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to * I2C_DATAR register (I2C_SendData()). diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_misc.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_misc.c index bb5330bc..65108364 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_misc.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_misc.c @@ -2,7 +2,7 @@ * File Name : ch32x035_misc.c * Author : WCH * Version : V1.0.0 - * Date : 2023/04/06 + * Date : 2023/12/26 * Description : This file provides all the miscellaneous firmware functions . ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -20,15 +20,9 @@ __IO uint32_t NVIC_Priority_Group = 0; * * @param NVIC_PriorityGroup - specifies the priority grouping bits length. * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority - * 4 bits for subpriority - * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority * 3 bits for subpriority - * NVIC_PriorityGroup_2 - 2 bits for pre-emption priority + * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority * 2 bits for subpriority - * NVIC_PriorityGroup_3 - 3 bits for pre-emption priority - * 1 bits for subpriority - * NVIC_PriorityGroup_4 - 4 bits for pre-emption priority - * 0 bits for subpriority * * @return none */ @@ -45,58 +39,36 @@ void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) * * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the * configuration information for the specified NVIC peripheral. + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 7. * * @return none */ void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) { - uint8_t tmppre = 0; - +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) if(NVIC_Priority_Group == NVIC_PriorityGroup_0) { NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_1) +#else + if(NVIC_Priority_Group == NVIC_PriorityGroup_1) { if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); - } - else - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); - } - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_2) - { - if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1) - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); - } - else - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2)); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5)); } - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_3) - { - if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3) + else if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 0) { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5)); } - else - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4)); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); - } - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_4) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4); } +#endif if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) { diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_opa.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_opa.c index 94a4f0da..ef6804f7 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_opa.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_opa.c @@ -137,6 +137,7 @@ void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) | (OPA_InitStruct->RST_EN << 4) | (OPA_InitStruct->BKIN_SEL << 6) | (OPA_InitStruct->OUT_IE << 8) | (OPA_InitStruct->CNT_IE << 10) | (OPA_InitStruct->NMI_IE << 11); + tmp1 &= 0xFF00; tmp1 |= OPA_InitStruct->OPA_POLL_Interval; OPA->CFGR1 = tmp0; @@ -244,7 +245,7 @@ void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct) void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct) { CMP_InitStruct->CMP_NUM = CMP1; - CMP_InitStruct->Mode = OUT_IO_TIM2_CH1; + CMP_InitStruct->Mode = OUT_IO_TIM2; CMP_InitStruct->NSEL = CMP_CHN0; CMP_InitStruct->PSEL = CMP_CHP1; CMP_InitStruct->HYEN = CMP_HYEN1; diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_pwr.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_pwr.c index 9c1295c4..c90ce357 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_pwr.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_pwr.c @@ -2,7 +2,7 @@ * File Name : ch32x035_pwr.c * Author : WCH * Version : V1.0.0 - * Date : 2023/04/06 + * Date : 2024/06/14 * Description : This file provides all the PWR firmware functions. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -38,10 +38,10 @@ void PWR_DeInit(void) * Detector(PVD). * * @param PWR_PVDLevel - specifies the PVD detection level - * PWR_PVDLevel_2V1 - PVD detection level set to 2.1V - * PWR_PVDLevel_2V3 - PVD detection level set to 2.3V - * PWR_PVDLevel_3V0 - PVD detection level set to 3.0V - * PWR_PVDLevel_4V0 - PVD detection level set to 4.0V + * PWR_PVDLevel_0 - PVD detection level set to mode 0 + * PWR_PVDLevel_1 - PVD detection level set to mode 1 + * PWR_PVDLevel_2 - PVD detection level set to mode 2 + * PWR_PVDLevel_3 - PVD detection level set to mode 3 * * @return none */ @@ -110,7 +110,7 @@ void PWR_EnterSTANDBYMode(void) * PWR_FLAG_PVDO - PVD Output * PWR_FLAG_FLASH - Flash low power flag * - * @return none + * @return The new state of PWR_FLAG (SET or RESET). */ FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) { @@ -127,4 +127,30 @@ FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) return bitstatus; } +/********************************************************************* + * @fn PWR_VDD_SupplyVoltage + * + * @brief Checks VDD Supply Voltage. + * + * @param none + * + * @return PWR_VDD - VDD Supply Voltage. + * PWR_VDD_5V - VDD = 5V + * PWR_VDD_3V3 - VDD = 3.3V + */ +PWR_VDD PWR_VDD_SupplyVoltage(void) +{ + PWR_VDD VDD_Voltage = PWR_VDD_3V3; + Delay_Init(); + RCC_APB1PeriphClockCmd( RCC_APB1Periph_PWR, ENABLE); + PWR_PVDLevelConfig(PWR_PVDLevel_3); + Delay_Us(10); + if( PWR_GetFlagStatus(PWR_FLAG_PVDO) == (uint32_t)RESET) + { + VDD_Voltage = PWR_VDD_5V; + } + PWR_PVDLevelConfig(PWR_PVDLevel_0); + + return VDD_Voltage; +} diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_spi.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_spi.c index 7a79142c..9f1c3348 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_spi.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_spi.c @@ -2,7 +2,7 @@ * File Name : ch32x035_spi.c * Author : WCH * Version : V1.0.0 - * Date : 2023/04/06 + * Date : 2024/06/05 * Description : This file provides all the SPI firmware functions. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -53,7 +53,8 @@ void SPI_I2S_DeInit(SPI_TypeDef *SPIx) * @fn SPI_Init * * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. + * parameters in the SPI_InitStruct. + * When using SPI slave mode to send data, the CPOL bit should be set to 1. * * @param SPIx - where x can be 1 to select the SPI peripheral. * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_tim.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_tim.c index 9f6f1b16..9f69f926 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_tim.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_tim.c @@ -2,7 +2,7 @@ * File Name : ch32x035_tim.c * Author : WCH * Version : V1.0.0 - * Date : 2023/04/06 + * Date : 2023/12/26 * Description : This file provides all the TIM firmware functions. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -862,7 +862,7 @@ void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) * * @brief Configures the TIMx Encoder Interface. * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. * TIM_EncoderMode - specifies the TIMx Encoder Mode. * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending * on TI2FP2 level. @@ -2336,7 +2336,7 @@ static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ } else { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC4NP)); + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E); } diff --git a/system/CH32X035/SRC/Startup/startup_ch32x035.S b/system/CH32X035/SRC/Startup/startup_ch32x035.S index 84b4203f..3883a4a7 100644 --- a/system/CH32X035/SRC/Startup/startup_ch32x035.S +++ b/system/CH32X035/SRC/Startup/startup_ch32x035.S @@ -1,8 +1,8 @@ ;/********************************** (C) COPYRIGHT ******************************* ;* File Name : startup_ch32x035.s ;* Author : WCH -;* Version : V1.0.0 -;* Date : 2023/04/06 +;* Version : V1.0.1 +;* Date : 2023/12/06 ;* Description : vector table for eclipse toolchain. ;********************************************************************************* ;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -15,6 +15,7 @@ .align 1 _start: j handle_reset + .section .vector,"ax",@progbits .align 1 _vector_base: @@ -77,7 +78,6 @@ _vector_base: .word TIM3_IRQHandler /* TIM3 */ .option rvc; - .section .text.vector_handler, "ax", @progbits .weak NMI_Handler /* NMI */ .weak HardFault_Handler /* Hard Fault */ @@ -125,51 +125,53 @@ _vector_base: .weak TIM2_BRK_IRQHandler /* TIM2 Break */ .weak TIM3_IRQHandler /* TIM3 */ -NMI_Handler: 1: j 1b -HardFault_Handler: 1: j 1b -Ecall_M_Mode_Handler: 1: j 1b -Ecall_U_Mode_Handler: 1: j 1b -Break_Point_Handler: 1: j 1b -SysTick_Handler: 1: j 1b -SW_Handler: 1: j 1b -WWDG_IRQHandler: 1: j 1b -PVD_IRQHandler: 1: j 1b -FLASH_IRQHandler: 1: j 1b -EXTI7_0_IRQHandler: 1: j 1b -AWU_IRQHandler: 1: j 1b -DMA1_Channel1_IRQHandler: 1: j 1b -DMA1_Channel2_IRQHandler: 1: j 1b -DMA1_Channel3_IRQHandler: 1: j 1b -DMA1_Channel4_IRQHandler: 1: j 1b -DMA1_Channel5_IRQHandler: 1: j 1b -DMA1_Channel6_IRQHandler: 1: j 1b -DMA1_Channel7_IRQHandler: 1: j 1b -ADC1_IRQHandler: 1: j 1b -I2C1_EV_IRQHandler: 1: j 1b -I2C1_ER_IRQHandler: 1: j 1b -USART1_IRQHandler: 1: j 1b -SPI1_IRQHandler: 1: j 1b -TIM1_BRK_IRQHandler: 1: j 1b -TIM1_UP_IRQHandler: 1: j 1b -TIM1_TRG_COM_IRQHandler: 1: j 1b -TIM1_CC_IRQHandler: 1: j 1b -TIM2_UP_IRQHandler: 1: j 1b -USART2_IRQHandler: 1: j 1b -EXTI15_8_IRQHandler: 1: j 1b -EXTI25_16_IRQHandler: 1: j 1b -USART3_IRQHandler: 1: j 1b -USART4_IRQHandler: 1: j 1b -DMA1_Channel8_IRQHandler: 1: j 1b -USBFS_IRQHandler: 1: j 1b -USBFSWakeUp_IRQHandler: 1: j 1b -PIOC_IRQHandler: 1: j 1b -OPA_IRQHandler: 1: j 1b -USBPD_IRQHandler: 1: j 1b -USBPDWakeUp_IRQHandler: 1: j 1b -TIM2_CC_IRQHandler: 1: j 1b -TIM2_TRG_COM_IRQHandler: 1: j 1b -TIM2_BRK_IRQHandler: 1: j 1b -TIM3_IRQHandler: 1: j 1b +NMI_Handler: +HardFault_Handler: +Ecall_M_Mode_Handler: +Ecall_U_Mode_Handler: +Break_Point_Handler: +SysTick_Handler: +SW_Handler: +WWDG_IRQHandler: +PVD_IRQHandler: +FLASH_IRQHandler: +EXTI7_0_IRQHandler: +AWU_IRQHandler: +DMA1_Channel1_IRQHandler: +DMA1_Channel2_IRQHandler: +DMA1_Channel3_IRQHandler: +DMA1_Channel4_IRQHandler: +DMA1_Channel5_IRQHandler: +DMA1_Channel6_IRQHandler: +DMA1_Channel7_IRQHandler: +ADC1_IRQHandler: +I2C1_EV_IRQHandler: +I2C1_ER_IRQHandler: +USART1_IRQHandler: +SPI1_IRQHandler: +TIM1_BRK_IRQHandler: +TIM1_UP_IRQHandler: +TIM1_TRG_COM_IRQHandler: +TIM1_CC_IRQHandler: +TIM2_UP_IRQHandler: +USART2_IRQHandler: +EXTI15_8_IRQHandler: +EXTI25_16_IRQHandler: +USART3_IRQHandler: +USART4_IRQHandler: +DMA1_Channel8_IRQHandler: +USBFS_IRQHandler: +USBFSWakeUp_IRQHandler: +PIOC_IRQHandler: +OPA_IRQHandler: +USBPD_IRQHandler: +USBPDWakeUp_IRQHandler: +TIM2_CC_IRQHandler: +TIM2_TRG_COM_IRQHandler: +TIM2_BRK_IRQHandler: +TIM3_IRQHandler: +1: + j 1b .section .text.handle_reset,"ax",@progbits .weak handle_reset @@ -182,7 +184,7 @@ handle_reset: 1: la sp, _eusrstack 2: - /* Load data section from flash to RAM */ +/* Load data section from flash to RAM */ la a0, _data_lma la a1, _data_vma la a2, _edata @@ -194,7 +196,7 @@ handle_reset: addi a1, a1, 4 bltu a1, a2, 1b 2: - /* Clear bss section */ +/* Clear bss section */ la a0, _sbss la a1, _ebss bgeu a0, a1, 2f @@ -203,25 +205,20 @@ handle_reset: addi a0, a0, 4 bltu a0, a1, 1b 2: +/* Configure pipelining and instruction prediction */ li t0, 0x1f csrw 0xbc0, t0 - - /* Enable nested and hardware stack */ +/* Enable interrupt nesting and hardware stack */ li t0, 0x3 csrw 0x804, t0 - - /* Enable interrupt */ +/* Enable global interrupt and configure privileged mode */ li t0, 0x88 - csrs mstatus, t0 - + csrw mstatus, t0 +/* Configure the interrupt vector table recognition mode and entry address mode */ la t0, _vector_base ori t0, t0, 3 csrw mtvec, t0 - la a0, __libc_fini_array - call atexit - call __libc_init_array - jal SystemInit la t0, main csrw mepc, t0 diff --git a/system/CH32X035/USER/ch32x035_it.c b/system/CH32X035/USER/ch32x035_it.c index e4301bdd..2d8643fb 100644 --- a/system/CH32X035/USER/ch32x035_it.c +++ b/system/CH32X035/USER/ch32x035_it.c @@ -2,7 +2,7 @@ * File Name : ch32x035_it.c * Author : WCH * Version : V1.0.0 - * Date : 2023/04/06 + * Date : 2024/10/28 * Description : Main Interrupt Service Routines. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -23,6 +23,9 @@ void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void NMI_Handler(void) { + while (1) + { + } } /********************************************************************* @@ -34,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } From 68415ed888d19c838a43f88a053830034667f163 Mon Sep 17 00:00:00 2001 From: Koki Mizumoto <21km43@gmail.com> Date: Sat, 11 Jan 2025 11:03:04 +0900 Subject: [PATCH 19/20] CH32X035 cannot manually set GPIO to open drain --- cores/arduino/ch32/pinmap.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/cores/arduino/ch32/pinmap.c b/cores/arduino/ch32/pinmap.c index 07a40047..8d4f85ec 100644 --- a/cores/arduino/ch32/pinmap.c +++ b/cores/arduino/ch32/pinmap.c @@ -130,15 +130,19 @@ void pin_function(PinName pin, int function) case CH_CNF_OUTPUT_PP: GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; break; +#if !defined(CH32X035) case CH_CNF_OUTPUT_OD: GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD; break; +#endif case CH_CNF_OUTPUT_AFPP: GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; break; +#if !defined(CH32X035) case CH_CNF_OUTPUT_AFOD: GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD; - break; + break; +#endif default: GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; break; From 2311417665aa90b8b44829f1db958555bc5f3bc4 Mon Sep 17 00:00:00 2001 From: Koki Mizumoto <21km43@gmail.com> Date: Sat, 11 Jan 2025 11:24:27 +0900 Subject: [PATCH 20/20] add _fini, _init --- system/CH32L10x/SRC/Debug/debug.c | 3 +++ system/CH32X035/SRC/Debug/debug.c | 7 +++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/system/CH32L10x/SRC/Debug/debug.c b/system/CH32L10x/SRC/Debug/debug.c index 76433342..81a5334a 100644 --- a/system/CH32L10x/SRC/Debug/debug.c +++ b/system/CH32L10x/SRC/Debug/debug.c @@ -190,3 +190,6 @@ void *_sbrk(ptrdiff_t incr) curbrk += incr; return curbrk - incr; } + +void _fini() {} +void _init() {} diff --git a/system/CH32X035/SRC/Debug/debug.c b/system/CH32X035/SRC/Debug/debug.c index 0f083858..855593b8 100644 --- a/system/CH32X035/SRC/Debug/debug.c +++ b/system/CH32X035/SRC/Debug/debug.c @@ -181,8 +181,8 @@ int _write(int fd, char *buf, int size) { /** - * data0 data1 ¹²8¸ö×Ö½Ú - * data0×îµÍλµÄ×Ö½Ú´æ·Å³¤¶È£¬×î´óΪ 7 + * data0 data1 ��8���ֽ� + * data0���λ���ֽڴ�ų��ȣ����Ϊ 7 * */ @@ -247,3 +247,6 @@ void *_sbrk(ptrdiff_t incr) curbrk += incr; return curbrk - incr; } + +void _fini() {} +void _init() {}