From e70a6afee7f7f0b99709d3750abca45532cc5769 Mon Sep 17 00:00:00 2001 From: tako Date: Mon, 26 May 2025 23:12:36 +0900 Subject: [PATCH 1/3] [CH32VM00X] Update USER directory with latest SDK * Clock was not set correctly due to flawed SYSCLK_FREQ logic. --- system/CH32VM00X/USER/ch32v00X_it.c | 3 +- system/CH32VM00X/USER/system_ch32v00X.c | 55 ++++++++++++++++--------- 2 files changed, 37 insertions(+), 21 deletions(-) diff --git a/system/CH32VM00X/USER/ch32v00X_it.c b/system/CH32VM00X/USER/ch32v00X_it.c index 91f92f38..8b493072 100644 --- a/system/CH32VM00X/USER/ch32v00X_it.c +++ b/system/CH32VM00X/USER/ch32v00X_it.c @@ -2,7 +2,7 @@ * File Name : ch32v00X_it.c * Author : WCH * Version : V1.0.0 - * Date : 2024/01/01 + * Date : 2024/11/04 * Description : Main Interrupt Service Routines. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/system/CH32VM00X/USER/system_ch32v00X.c b/system/CH32VM00X/USER/system_ch32v00X.c index 6169b774..e1119279 100644 --- a/system/CH32VM00X/USER/system_ch32v00X.c +++ b/system/CH32VM00X/USER/system_ch32v00X.c @@ -2,7 +2,7 @@ * File Name : system_ch32v00X.c * Author : WCH * Version : V1.0.0 - * Date : 2024/01/01 + * Date : 2024/11/04 * Description : CH32V00X Device Peripheral Access Layer System Source File. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -18,8 +18,8 @@ */ //#define SYSCLK_FREQ_8MHz_HSI 8000000 -//#define SYSCLK_FREQ_24MHz_HSI HSI_VALUE -//#define SYSCLK_FREQ_48MHz_HSI 48000000 +//#define SYSCLK_FREQ_24MHZ_HSI HSI_VALUE +#define SYSCLK_FREQ_48MHZ_HSI 48000000 //#define SYSCLK_FREQ_8MHz_HSE 8000000 //#define SYSCLK_FREQ_24MHz_HSE HSE_VALUE //#define SYSCLK_FREQ_48MHz_HSE 48000000 @@ -27,10 +27,10 @@ /* Clock Definitions */ #ifdef SYSCLK_FREQ_8MHz_HSI uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_24MHz_HSI - uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz_HSI - uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHZ_HSI + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHZ_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHZ_HSI + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHZ_HSI; /* System Clock Frequency (Core Clock) */ #elif defined SYSCLK_FREQ_8MHz_HSE uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSE; /* System Clock Frequency (Core Clock) */ #elif defined SYSCLK_FREQ_24MHz_HSE @@ -49,10 +49,10 @@ static void SetSysClock(void); #ifdef SYSCLK_FREQ_8MHz_HSI static void SetSysClockTo_8MHz_HSI(void); -#elif defined SYSCLK_FREQ_24MHz_HSI - static void SetSysClockTo_24MHz_HSI(void); -#elif defined SYSCLK_FREQ_48MHz_HSI - static void SetSysClockTo_48MHz_HSI(void); +#elif defined SYSCLK_FREQ_24MHZ_HSI + static void SetSysClockTo_24MHZ_HSI(void); +#elif defined SYSCLK_FREQ_48MHZ_HSI + static void SetSysClockTo_48MHZ_HSI(void); #elif defined SYSCLK_FREQ_8MHz_HSE static void SetSysClockTo_8MHz_HSE(void); #elif defined SYSCLK_FREQ_24MHz_HSE @@ -80,8 +80,8 @@ void SystemInit (void) RCC->CFGR0 &= (uint32_t)0x68FF0000; tmp = RCC->CTLR; - tmp &= (uint32_t)0xFE16FFFB; - tmp |= (uint32_t)(1<<22)|(1<<20); + tmp &= (uint32_t)0xFED6FFFB; + tmp |= (uint32_t)(1<<20); RCC->CTLR = tmp; RCC->CTLR &= (uint32_t)0xFFFBFFFF; @@ -194,7 +194,7 @@ static void SetSysClockTo_8MHz_HSI(void) FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_0; } -#elif defined SYSCLK_FREQ_24MHz_HSI +#elif defined SYSCLK_FREQ_24MHZ_HSI /********************************************************************* * @fn SetSysClockTo_24MHZ_HSI @@ -203,7 +203,7 @@ static void SetSysClockTo_8MHz_HSI(void) * * @return none */ -static void SetSysClockTo_24MHz_HSI(void) +static void SetSysClockTo_24MHZ_HSI(void) { /* HCLK = SYSCLK = PB1 */ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; @@ -213,7 +213,7 @@ static void SetSysClockTo_24MHz_HSI(void) } -#elif defined SYSCLK_FREQ_48MHz_HSI +#elif defined SYSCLK_FREQ_48MHZ_HSI /********************************************************************* * @fn SetSysClockTo_48MHZ_HSI @@ -222,7 +222,7 @@ static void SetSysClockTo_24MHz_HSI(void) * * @return none */ -static void SetSysClockTo_48MHz_HSI(void) +static void SetSysClockTo_48MHZ_HSI(void) { /* HCLK = SYSCLK = PB1 */ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; @@ -302,8 +302,13 @@ static void SetSysClockTo_8MHz_HSE(void) { /* * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error + * configuration. User can add here some code to deal with this error */ + /* Open PA1-PA2 GPIO function */ + AFIO->PCFR1 &= ~(1<<17); + RCC->PB2PCENR &= ~RCC_AFIOEN; + + RCC->CTLR &= ((uint32_t)~RCC_HSEON); } } @@ -361,8 +366,13 @@ static void SetSysClockTo_24MHz_HSE(void) { /* * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error + * configuration. User can add here some code to deal with this error */ + /* Open PA1-PA2 GPIO function */ + AFIO->PCFR1 &= ~(1<<17); + RCC->PB2PCENR &= ~RCC_AFIOEN; + + RCC->CTLR &= ((uint32_t)~RCC_HSEON); } } @@ -430,8 +440,13 @@ static void SetSysClockTo_48MHz_HSE(void) { /* * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error + * configuration. User can add here some code to deal with this error */ + /* Open PA1-PA2 GPIO function */ + AFIO->PCFR1 &= ~(1<<17); + RCC->PB2PCENR &= ~RCC_AFIOEN; + + RCC->CTLR &= ((uint32_t)~RCC_HSEON); } } #endif From ddbf9108d8238ca20faf98cb9c8db165df678041 Mon Sep 17 00:00:00 2001 From: tako0910 Date: Tue, 27 May 2025 11:27:22 +0900 Subject: [PATCH 2/3] [CH32VM00X] uncomment SYSCLK_FREQ define * This definition is defined from the IDE side and should not be defined here. --- system/CH32VM00X/USER/system_ch32v00X.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/system/CH32VM00X/USER/system_ch32v00X.c b/system/CH32VM00X/USER/system_ch32v00X.c index e1119279..c4b8e7d6 100644 --- a/system/CH32VM00X/USER/system_ch32v00X.c +++ b/system/CH32VM00X/USER/system_ch32v00X.c @@ -19,7 +19,7 @@ //#define SYSCLK_FREQ_8MHz_HSI 8000000 //#define SYSCLK_FREQ_24MHZ_HSI HSI_VALUE -#define SYSCLK_FREQ_48MHZ_HSI 48000000 +//#define SYSCLK_FREQ_48MHZ_HSI 48000000 //#define SYSCLK_FREQ_8MHz_HSE 8000000 //#define SYSCLK_FREQ_24MHz_HSE HSE_VALUE //#define SYSCLK_FREQ_48MHz_HSE 48000000 From 7601e26e67d17f1ad26ced9b55034bace2bced4c Mon Sep 17 00:00:00 2001 From: tako0910 Date: Tue, 27 May 2025 11:41:38 +0900 Subject: [PATCH 3/3] [CH32VM00X] adjusted clock definitions to the SDK side --- boards.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/boards.txt b/boards.txt index 32fbe00a..3ad57d06 100644 --- a/boards.txt +++ b/boards.txt @@ -159,10 +159,11 @@ CH32VM00X_EVT.menu.upload_method.ispMethod.upload.tool=wchisp # Clock Select +# (Some of the ""MHz"" and ""MHZ"" notations are mixed, but this is to match the definitions on the SDK side.) CH32VM00X_EVT.menu.clock.48MHz_HSI=48MHz Internal -CH32VM00X_EVT.menu.clock.48MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSI=48000000 -DF_CPU=48000000 +CH32VM00X_EVT.menu.clock.48MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_48MHZ_HSI=48000000 -DF_CPU=48000000 CH32VM00X_EVT.menu.clock.24MHz_HSI=24MHz Internal -CH32VM00X_EVT.menu.clock.24MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_24MHz_HSI=24000000 -DF_CPU=24000000 +CH32VM00X_EVT.menu.clock.24MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_24MHZ_HSI=24000000 -DF_CPU=24000000 CH32VM00X_EVT.menu.clock.8MHz_HSI=8MHz Internal CH32VM00X_EVT.menu.clock.8MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_8MHz_HSI=8000000 -DF_CPU=8000000 CH32VM00X_EVT.menu.clock.48MHz_HSE=48MHz External