|
| 1 | +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py |
| 2 | + |
| 3 | +// The script is designed to make adding checks to |
| 4 | +// a test case fast, it is *not* designed to be authoritative |
| 5 | +// about what constitutes a good test! The CHECK should be |
| 6 | +// minimized and named to reflect the test intent. |
| 7 | + |
| 8 | +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py |
| 9 | + |
| 10 | +// The script is designed to make adding checks to |
| 11 | +// a test case fast, it is *not* designed to be authoritative |
| 12 | +// minimized and named to reflect the test intent. |
| 13 | + |
| 14 | +// RUN: stablehlo-opt %s --stablehlo-legalize-to-vhlo=allow-other-dialects | FileCheck %s |
| 15 | +// RUN: stablehlo-opt %s > %t.0 |
| 16 | +// RUN: stablehlo-opt %s --stablehlo-legalize-to-vhlo=allow-other-dialects | stablehlo-opt --vhlo-legalize-to-stablehlo > %t.1 |
| 17 | +// RUN: diff %t.0 %t.1 |
| 18 | + |
| 19 | +// CHECK-LABEL: vhlo.func_v1 @op_other( |
| 20 | +// CHECK-SAME: %[[VAL_0:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: !vhlo.tensor_v1<!vhlo.f32_v1>) -> (!vhlo.tensor_v1<!vhlo.f32_v1>) { |
| 21 | +// CHECK: %[[VAL_1:.*]] = builtin.unrealized_conversion_cast %[[VAL_0]] : !vhlo.tensor_v1<!vhlo.f32_v1> to tensor<f32> |
| 22 | +// CHECK: %[[VAL_2:.*]] = arith.addf %[[VAL_1]], %[[VAL_1]] : tensor<f32> |
| 23 | +// CHECK: %[[VAL_3:.*]] = builtin.unrealized_conversion_cast %[[VAL_2]] : tensor<f32> to !vhlo.tensor_v1<!vhlo.f32_v1> |
| 24 | +// CHECK: "vhlo.return_v1"(%[[VAL_3]]) : (!vhlo.tensor_v1<!vhlo.f32_v1>) -> () |
| 25 | +// CHECK: } |
| 26 | +func.func @op_other(%arg0: tensor<f32>) -> tensor<f32> { |
| 27 | + %0 = arith.addf %arg0, %arg0 : tensor<f32> |
| 28 | + return %0 : tensor<f32> |
| 29 | +} |
| 30 | + |
| 31 | +// ----- |
| 32 | + |
| 33 | +// CHECK-LABEL: vhlo.func_v1 @op_shlo( |
| 34 | +// CHECK-SAME: %[[VAL_0:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: !vhlo.tensor_v1<!vhlo.f32_v1>) -> (!vhlo.tensor_v1<!vhlo.f32_v1>) { |
| 35 | +// CHECK: %[[VAL_1:.*]] = "vhlo.add_v1"(%[[VAL_0]], %[[VAL_0]]) : (!vhlo.tensor_v1<!vhlo.f32_v1>, !vhlo.tensor_v1<!vhlo.f32_v1>) -> !vhlo.tensor_v1<!vhlo.f32_v1> |
| 36 | +// CHECK: "vhlo.return_v1"(%[[VAL_1]]) : (!vhlo.tensor_v1<!vhlo.f32_v1>) -> () |
| 37 | +// CHECK: } |
| 38 | +func.func @op_shlo(%arg0: tensor<f32>) -> tensor<f32> { |
| 39 | + %0 = stablehlo.add %arg0, %arg0 : tensor<f32> |
| 40 | + return %0 : tensor<f32> |
| 41 | +} |
| 42 | + |
| 43 | +// ----- |
| 44 | + |
| 45 | +// CHECK-LABEL: vhlo.func_v1 @mixed_shlo_other_shlo( |
| 46 | +// CHECK-SAME: %[[VAL_0:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: !vhlo.tensor_v1<!vhlo.f32_v1>) -> (!vhlo.tensor_v1<!vhlo.f32_v1>) { |
| 47 | +// CHECK: %[[VAL_1:.*]] = builtin.unrealized_conversion_cast %[[VAL_0]] : !vhlo.tensor_v1<!vhlo.f32_v1> to tensor<f32> |
| 48 | +// CHECK: %[[VAL_2:.*]] = "vhlo.abs_v1"(%[[VAL_0]]) : (!vhlo.tensor_v1<!vhlo.f32_v1>) -> !vhlo.tensor_v1<!vhlo.f32_v1> |
| 49 | +// CHECK: %[[VAL_3:.*]] = builtin.unrealized_conversion_cast %[[VAL_2]] : !vhlo.tensor_v1<!vhlo.f32_v1> to tensor<f32> |
| 50 | +// CHECK: %[[VAL_4:.*]] = arith.addf %[[VAL_3]], %[[VAL_1]] : tensor<f32> |
| 51 | +// CHECK: %[[VAL_5:.*]] = builtin.unrealized_conversion_cast %[[VAL_4]] : tensor<f32> to !vhlo.tensor_v1<!vhlo.f32_v1> |
| 52 | +// CHECK: %[[VAL_6:.*]] = "vhlo.abs_v1"(%[[VAL_5]]) : (!vhlo.tensor_v1<!vhlo.f32_v1>) -> !vhlo.tensor_v1<!vhlo.f32_v1> |
| 53 | +// CHECK: "vhlo.return_v1"(%[[VAL_6]]) : (!vhlo.tensor_v1<!vhlo.f32_v1>) -> () |
| 54 | +// CHECK: } |
| 55 | +func.func @mixed_shlo_other_shlo(%arg0: tensor<f32>) -> tensor<f32> { |
| 56 | + %0 = stablehlo.abs %arg0 : tensor<f32> |
| 57 | + %1 = arith.addf %0, %arg0 : tensor<f32> |
| 58 | + %2 = stablehlo.abs %1 : tensor<f32> |
| 59 | + return %2 : tensor<f32> |
| 60 | +} |
| 61 | + |
| 62 | +// ----- |
| 63 | + |
| 64 | +// CHECK-LABEL: vhlo.func_v1 @mixed_other_shlo_other( |
| 65 | +// CHECK-SAME: %[[VAL_0:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: !vhlo.tensor_v1<!vhlo.f32_v1>) -> (!vhlo.tensor_v1<!vhlo.f32_v1>) { |
| 66 | +// CHECK: %[[VAL_1:.*]] = builtin.unrealized_conversion_cast %[[VAL_0]] : !vhlo.tensor_v1<!vhlo.f32_v1> to tensor<f32> |
| 67 | +// CHECK: %[[VAL_2:.*]] = arith.addf %[[VAL_1]], %[[VAL_1]] : tensor<f32> |
| 68 | +// CHECK: %[[VAL_3:.*]] = builtin.unrealized_conversion_cast %[[VAL_2]] : tensor<f32> to !vhlo.tensor_v1<!vhlo.f32_v1> |
| 69 | +// CHECK: %[[VAL_4:.*]] = "vhlo.add_v1"(%[[VAL_3]], %[[VAL_0]]) : (!vhlo.tensor_v1<!vhlo.f32_v1>, !vhlo.tensor_v1<!vhlo.f32_v1>) -> !vhlo.tensor_v1<!vhlo.f32_v1> |
| 70 | +// CHECK: %[[VAL_5:.*]] = builtin.unrealized_conversion_cast %[[VAL_4]] : !vhlo.tensor_v1<!vhlo.f32_v1> to tensor<f32> |
| 71 | +// CHECK: %[[VAL_6:.*]] = arith.addf %[[VAL_5]], %[[VAL_1]] : tensor<f32> |
| 72 | +// CHECK: %[[VAL_7:.*]] = builtin.unrealized_conversion_cast %[[VAL_6]] : tensor<f32> to !vhlo.tensor_v1<!vhlo.f32_v1> |
| 73 | +// CHECK: "vhlo.return_v1"(%[[VAL_7]]) : (!vhlo.tensor_v1<!vhlo.f32_v1>) -> () |
| 74 | +// CHECK: } |
| 75 | +func.func @mixed_other_shlo_other(%arg0: tensor<f32>) -> tensor<f32> { |
| 76 | + %0 = arith.addf %arg0, %arg0 : tensor<f32> |
| 77 | + %1 = stablehlo.add %0, %arg0 : tensor<f32> |
| 78 | + %2 = arith.addf %1, %arg0 : tensor<f32> |
| 79 | + return %2 : tensor<f32> |
| 80 | +} |
| 81 | + |
| 82 | +// ----- |
| 83 | + |
| 84 | +// CHECK-LABEL: vhlo.func_v1 @op_with_region( |
| 85 | +// CHECK-SAME: %[[VAL_0:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: !vhlo.tensor_v1<1x16x16x320x!vhlo.f32_v1>, |
| 86 | +// CHECK-SAME: %[[VAL_1:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: !vhlo.tensor_v1<!vhlo.f32_v1>) -> (!vhlo.tensor_v1<1x320x!vhlo.f32_v1>) { |
| 87 | +// CHECK: %[[VAL_2:.*]] = "vhlo.reduce_v1"(%[[VAL_0]], %[[VAL_1]]) <{dimensions = #{{.*}}<dense<[1, 2]> : tensor<2xi64>>}> ({ |
| 88 | +// CHECK: ^bb0(%[[VAL_3:.*]]: !vhlo.tensor_v1<!vhlo.f32_v1>, %[[VAL_4:.*]]: !vhlo.tensor_v1<!vhlo.f32_v1>): |
| 89 | +// CHECK: %[[VAL_5:.*]] = "vhlo.add_v1"(%[[VAL_3]], %[[VAL_4]]) : (!vhlo.tensor_v1<!vhlo.f32_v1>, !vhlo.tensor_v1<!vhlo.f32_v1>) -> !vhlo.tensor_v1<!vhlo.f32_v1> |
| 90 | +// CHECK: "vhlo.return_v1"(%[[VAL_5]]) : (!vhlo.tensor_v1<!vhlo.f32_v1>) -> () |
| 91 | +// CHECK: }) : (!vhlo.tensor_v1<1x16x16x320x!vhlo.f32_v1>, !vhlo.tensor_v1<!vhlo.f32_v1>) -> !vhlo.tensor_v1<1x320x!vhlo.f32_v1> |
| 92 | +// CHECK: "vhlo.return_v1"(%[[VAL_2]]) : (!vhlo.tensor_v1<1x320x!vhlo.f32_v1>) -> () |
| 93 | +// CHECK: } |
| 94 | +func.func @op_with_region(%arg0: tensor<1x16x16x320xf32>, %arg1: tensor<f32>) -> tensor<1x320xf32> { |
| 95 | + %0 = stablehlo.reduce(%arg0 init: %arg1) applies stablehlo.add across dimensions = [1, 2] : (tensor<1x16x16x320xf32>, tensor<f32>) -> tensor<1x320xf32> |
| 96 | + return %0 : tensor<1x320xf32> |
| 97 | +} |
| 98 | + |
| 99 | +// ----- |
| 100 | + |
| 101 | +// CHECK-LABEL: vhlo.func_v1 @op_with_region_mixed_other_shlo_other( |
| 102 | +// CHECK-SAME: %[[VAL_0:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: !vhlo.tensor_v1<7x5x!vhlo.f32_v1>, |
| 103 | +// CHECK-SAME: %[[VAL_1:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: !vhlo.tensor_v1<5x!vhlo.f32_v1>) -> (!vhlo.tensor_v1<5x!vhlo.f32_v1>) { |
| 104 | +// CHECK: %[[VAL_2:.*]] = "vhlo.reduce_v1"(%[[VAL_0]], %[[VAL_1]]) <{dimensions = #{{.*}}<dense<0> : tensor<1xi64>>}> ({ |
| 105 | +// CHECK: ^bb0(%[[VAL_3:.*]]: !vhlo.tensor_v1<5x!vhlo.f32_v1>, %[[VAL_4:.*]]: !vhlo.tensor_v1<5x!vhlo.f32_v1>): |
| 106 | +// CHECK: %[[VAL_5:.*]] = builtin.unrealized_conversion_cast %[[VAL_4]] : !vhlo.tensor_v1<5x!vhlo.f32_v1> to tensor<5xf32> |
| 107 | +// CHECK: %[[VAL_6:.*]] = builtin.unrealized_conversion_cast %[[VAL_3]] : !vhlo.tensor_v1<5x!vhlo.f32_v1> to tensor<5xf32> |
| 108 | +// CHECK: %[[VAL_7:.*]] = arith.addf %[[VAL_6]], %[[VAL_5]] : tensor<5xf32> |
| 109 | +// CHECK: %[[VAL_8:.*]] = builtin.unrealized_conversion_cast %[[VAL_7]] : tensor<5xf32> to !vhlo.tensor_v1<5x!vhlo.f32_v1> |
| 110 | +// CHECK: %[[VAL_9:.*]] = "vhlo.add_v1"(%[[VAL_8]], %[[VAL_3]]) : (!vhlo.tensor_v1<5x!vhlo.f32_v1>, !vhlo.tensor_v1<5x!vhlo.f32_v1>) -> !vhlo.tensor_v1<5x!vhlo.f32_v1> |
| 111 | +// CHECK: %[[VAL_10:.*]] = builtin.unrealized_conversion_cast %[[VAL_9]] : !vhlo.tensor_v1<5x!vhlo.f32_v1> to tensor<5xf32> |
| 112 | +// CHECK: %[[VAL_11:.*]] = arith.addf %[[VAL_10]], %[[VAL_5]] : tensor<5xf32> |
| 113 | +// CHECK: %[[VAL_12:.*]] = builtin.unrealized_conversion_cast %[[VAL_11]] : tensor<5xf32> to !vhlo.tensor_v1<5x!vhlo.f32_v1> |
| 114 | +// CHECK: "vhlo.return_v1"(%[[VAL_12]]) : (!vhlo.tensor_v1<5x!vhlo.f32_v1>) -> () |
| 115 | +// CHECK: }) : (!vhlo.tensor_v1<7x5x!vhlo.f32_v1>, !vhlo.tensor_v1<5x!vhlo.f32_v1>) -> !vhlo.tensor_v1<5x!vhlo.f32_v1> |
| 116 | +// CHECK: "vhlo.return_v1"(%[[VAL_2]]) : (!vhlo.tensor_v1<5x!vhlo.f32_v1>) -> () |
| 117 | +// CHECK: } |
| 118 | +func.func @op_with_region_mixed_other_shlo_other(%arg0: tensor<7x5xf32>, %arg1: tensor<5xf32>) -> tensor<5xf32> { |
| 119 | + %0 = stablehlo.reduce(%arg0 init: %arg1) across dimensions = [0] : (tensor<7x5xf32>, tensor<5xf32>) -> tensor<5xf32> |
| 120 | + reducer(%arg2: tensor<5xf32>, %arg3: tensor<5xf32>) { |
| 121 | + %1 = arith.addf %arg2, %arg3 : tensor<5xf32> |
| 122 | + %2 = stablehlo.add %1, %arg2 : tensor<5xf32> |
| 123 | + %3 = arith.addf %2, %arg3 : tensor<5xf32> |
| 124 | + stablehlo.return %3 : tensor<5xf32> |
| 125 | + } |
| 126 | + return %0 : tensor<5xf32> |
| 127 | +} |
| 128 | + |
| 129 | +// ----- |
| 130 | + |
| 131 | +// CHECK-LABEL: vhlo.func_v1 @op_with_region_mixed_shlo_other_shlo( |
| 132 | +// CHECK-SAME: %[[VAL_0:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: !vhlo.tensor_v1<7x5x!vhlo.f32_v1>, |
| 133 | +// CHECK-SAME: %[[VAL_1:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: !vhlo.tensor_v1<5x!vhlo.f32_v1>) -> (!vhlo.tensor_v1<5x!vhlo.f32_v1>) { |
| 134 | +// CHECK: %[[VAL_2:.*]] = "vhlo.reduce_v1"(%[[VAL_0]], %[[VAL_1]]) <{dimensions = #{{.*}}<dense<0> : tensor<1xi64>>}> ({ |
| 135 | +// CHECK: ^bb0(%[[VAL_3:.*]]: !vhlo.tensor_v1<5x!vhlo.f32_v1>, %[[VAL_4:.*]]: !vhlo.tensor_v1<5x!vhlo.f32_v1>): |
| 136 | +// CHECK: %[[VAL_5:.*]] = builtin.unrealized_conversion_cast %[[VAL_4]] : !vhlo.tensor_v1<5x!vhlo.f32_v1> to tensor<5xf32> |
| 137 | +// CHECK: %[[VAL_6:.*]] = "vhlo.abs_v1"(%[[VAL_3]]) : (!vhlo.tensor_v1<5x!vhlo.f32_v1>) -> !vhlo.tensor_v1<5x!vhlo.f32_v1> |
| 138 | +// CHECK: %[[VAL_7:.*]] = builtin.unrealized_conversion_cast %[[VAL_6]] : !vhlo.tensor_v1<5x!vhlo.f32_v1> to tensor<5xf32> |
| 139 | +// CHECK: %[[VAL_8:.*]] = arith.addf %[[VAL_7]], %[[VAL_5]] : tensor<5xf32> |
| 140 | +// CHECK: %[[VAL_9:.*]] = builtin.unrealized_conversion_cast %[[VAL_8]] : tensor<5xf32> to !vhlo.tensor_v1<5x!vhlo.f32_v1> |
| 141 | +// CHECK: %[[VAL_10:.*]] = "vhlo.abs_v1"(%[[VAL_9]]) : (!vhlo.tensor_v1<5x!vhlo.f32_v1>) -> !vhlo.tensor_v1<5x!vhlo.f32_v1> |
| 142 | +// CHECK: "vhlo.return_v1"(%[[VAL_10]]) : (!vhlo.tensor_v1<5x!vhlo.f32_v1>) -> () |
| 143 | +// CHECK: }) : (!vhlo.tensor_v1<7x5x!vhlo.f32_v1>, !vhlo.tensor_v1<5x!vhlo.f32_v1>) -> !vhlo.tensor_v1<5x!vhlo.f32_v1> |
| 144 | +// CHECK: "vhlo.return_v1"(%[[VAL_2]]) : (!vhlo.tensor_v1<5x!vhlo.f32_v1>) -> () |
| 145 | +// CHECK: } |
| 146 | +func.func @op_with_region_mixed_shlo_other_shlo(%arg0: tensor<7x5xf32>, %arg1: tensor<5xf32>) -> tensor<5xf32> { |
| 147 | + %0 = stablehlo.reduce(%arg0 init: %arg1) across dimensions = [0] : (tensor<7x5xf32>, tensor<5xf32>) -> tensor<5xf32> |
| 148 | + reducer(%arg2: tensor<5xf32>, %arg3: tensor<5xf32>) { |
| 149 | + %1 = stablehlo.abs %arg2 : tensor<5xf32> |
| 150 | + %2 = arith.addf %1, %arg3 : tensor<5xf32> |
| 151 | + %3 = stablehlo.abs %2 : tensor<5xf32> |
| 152 | + stablehlo.return %3 : tensor<5xf32> |
| 153 | + } |
| 154 | + return %0 : tensor<5xf32> |
| 155 | +} |
| 156 | + |
| 157 | +// ----- |
| 158 | + |
| 159 | +// CHECK-LABEL: vhlo.func_v1 @stablehlo_in_other_op_region( |
| 160 | +// CHECK-SAME: %[[VAL_0:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: !vhlo.tensor_v1<2x!vhlo.f32_v1>, |
| 161 | +// CHECK-SAME: %[[VAL_1:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: !vhlo.index_v1) -> (!vhlo.tensor_v1<2x!vhlo.f32_v1>) { |
| 162 | +// CHECK: %[[VAL_2:.*]] = builtin.unrealized_conversion_cast %[[VAL_0]] : !vhlo.tensor_v1<2x!vhlo.f32_v1> to tensor<2xf32> |
| 163 | +// CHECK: %[[VAL_3:.*]] = arith.constant 0 : index |
| 164 | +// CHECK: %[[VAL_4:.*]] = arith.constant 1 : index |
| 165 | +// CHECK: %[[VAL_5:.*]] = arith.constant 2 : index |
| 166 | +// CHECK: %[[VAL_6:.*]] = arith.constant 0.000000e+00 : f32 |
| 167 | +// CHECK: %[[VAL_7:.*]] = scf.for %[[VAL_8:.*]] = %[[VAL_3]] to %[[VAL_5]] step %[[VAL_4]] iter_args(%[[VAL_9:.*]] = %[[VAL_2]]) -> (tensor<2xf32>) { |
| 168 | +// CHECK: %[[VAL_10:.*]] = tensor.insert %[[VAL_6]] into %[[VAL_9]]{{\[}}%[[VAL_8]]] : tensor<2xf32> |
| 169 | +// CHECK: %[[VAL_11:.*]] = builtin.unrealized_conversion_cast %[[VAL_10]] : tensor<2xf32> to !vhlo.tensor_v1<2x!vhlo.f32_v1> |
| 170 | +// CHECK: %[[VAL_12:.*]] = "vhlo.add_v1"(%[[VAL_11]], %[[VAL_11]]) : (!vhlo.tensor_v1<2x!vhlo.f32_v1>, !vhlo.tensor_v1<2x!vhlo.f32_v1>) -> !vhlo.tensor_v1<2x!vhlo.f32_v1> |
| 171 | +// CHECK: %[[VAL_13:.*]] = builtin.unrealized_conversion_cast %[[VAL_12]] : !vhlo.tensor_v1<2x!vhlo.f32_v1> to tensor<2xf32> |
| 172 | +// CHECK: scf.yield %[[VAL_13]] : tensor<2xf32> |
| 173 | +// CHECK: } |
| 174 | +// CHECK: %[[VAL_14:.*]] = builtin.unrealized_conversion_cast %[[VAL_7]] : tensor<2xf32> to !vhlo.tensor_v1<2x!vhlo.f32_v1> |
| 175 | +// CHECK: "vhlo.return_v1"(%[[VAL_14]]) : (!vhlo.tensor_v1<2x!vhlo.f32_v1>) -> () |
| 176 | +// CHECK: } |
| 177 | +func.func @stablehlo_in_other_op_region(%arg0: tensor<2xf32>, %arg1: index) -> tensor<2xf32> { |
| 178 | + %c0 = arith.constant 0 : index |
| 179 | + %c1 = arith.constant 1 : index |
| 180 | + %c2 = arith.constant 2 : index |
| 181 | + %cst = arith.constant 0.0 : f32 |
| 182 | + |
| 183 | + %for = scf.for %i = %c0 to %c2 step %c1 iter_args(%arg2 = %arg0) -> tensor<2xf32> { |
| 184 | + %new_out = tensor.insert %cst into %arg2[%i] : tensor<2xf32> |
| 185 | + %new_out_add = stablehlo.add %new_out, %new_out : tensor<2xf32> |
| 186 | + scf.yield %new_out_add : tensor<2xf32> |
| 187 | + } |
| 188 | + return %for : tensor<2xf32> |
| 189 | +} |
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