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[BACKEND] Update LLVM version to llvm/llvm-project@4573c85
Updating floating point checks Adding missing Utility.h includes
1 parent d0cc81a commit 48b4b60

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19 files changed

+64
-48
lines changed

19 files changed

+64
-48
lines changed

‎cmake/llvm-hash.txt‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
c118864223c6309378cd704f3406533474c2759f
1+
4573c857da88b3210d497d9a88a89351a74b5964

‎include/triton/Conversion/MLIRTypes.h‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -28,15 +28,16 @@ inline Type bf16Ty(MLIRContext *ctx) { return BFloat16Type::get(ctx); }
2828

2929
inline bool isFloat(Type type) {
3030
return type.isF32() || type.isF64() || type.isF16() || type.isF128() ||
31-
type.isBF16() || type.isFloat8E4M3B11FNUZ() || type.isFloat8E4M3FN() ||
32-
type.isFloat8E4M3FNUZ() || type.isFloat8E5M2() ||
33-
type.isFloat8E5M2FNUZ();
31+
type.isBF16() ||
32+
llvm::isa<mlir::Float8E4M3B11FNUZType, mlir::Float8E4M3FNType,
33+
mlir::Float8E4M3FNUZType, mlir::Float8E5M2Type,
34+
mlir::Float8E5M2FNUZType>(type);
3435
}
3536

3637
inline bool isFloat8(Type type) {
37-
return type.isFloat8E4M3B11FNUZ() || type.isFloat8E4M3FN() ||
38-
type.isFloat8E4M3FNUZ() || type.isFloat8E5M2() ||
39-
type.isFloat8E5M2FNUZ();
38+
return llvm::isa<mlir::Float8E4M3B11FNUZType, mlir::Float8E4M3FNType,
39+
mlir::Float8E4M3FNUZType, mlir::Float8E5M2Type,
40+
mlir::Float8E5M2FNUZType>(type);
4041
}
4142

4243
inline bool isInt(Type type) { return type.isIntOrFloat() && !isFloat(type); }

‎lib/Analysis/Utility.cpp‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -732,14 +732,14 @@ bool supportMMA(triton::DotOp op, int version) {
732732
return false;
733733
if (!(numWarps % 4 == 0 && retShapePerCTA[rank - 2] % 64 == 0 &&
734734
retShapePerCTA[rank - 1] % 8 == 0 &&
735-
(aElemTy.isFloat8E5M2() || aElemTy.isFloat8E4M3FN() ||
735+
(llvm::isa<mlir::Float8E5M2Type, mlir::Float8E4M3FNType>(aElemTy) ||
736736
aElemTy.isInteger(8) || aElemTy.isF16() || aElemTy.isBF16() ||
737737
aElemTy.isF32()))) {
738738
return false;
739739
}
740740
// We cannot use MMA_V3 if we need to accumulate in F32 within the MMA op.
741741
if (op.getMaxNumImpreciseAcc() < 32 &&
742-
(aElemTy.isFloat8E5M2() || aElemTy.isFloat8E4M3FN()) &&
742+
(llvm::isa<mlir::Float8E5M2Type, mlir::Float8E4M3FNType>(aElemTy)) &&
743743
cast<RankedTensorType>(op.getType()).getElementType().isF32()) {
744744
return false;
745745
}
@@ -760,8 +760,9 @@ bool supportMMA(Value value, int version) {
760760
cast<triton::gpu::TensorOrMemDesc>(value.getType()).getElementType();
761761
// FP8 is not natively supported on all mma versions but it can always be
762762
// promoted to fp16 therefore we can always support it.
763-
bool isFP8 = elemTy.isFloat8E5M2() || elemTy.isFloat8E4M3FN() ||
764-
elemTy.isFloat8E5M2FNUZ() || elemTy.isFloat8E4M3FNUZ();
763+
bool isFP8 =
764+
llvm::isa<mlir::Float8E5M2Type, mlir::Float8E4M3FNType,
765+
mlir::Float8E5M2FNUZType, mlir::Float8E4M3FNUZType>(elemTy);
765766
return isFP8 || elemTy.isF16() || elemTy.isBF16() ||
766767
(elemTy.isF32() && version >= 2) ||
767768
(elemTy.isInteger(8) && version >= 2);

‎lib/Dialect/TritonGPU/Transforms/AccelerateMatmul.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -344,7 +344,8 @@ static void decomposeMixedModeDotOp(ModuleOp mod, int computeCapability) {
344344
NvidiaMmaEncodingAttr mmaLayout =
345345
dyn_cast<NvidiaMmaEncodingAttr>(D.getType().getEncoding());
346346
if (mmaLayout) {
347-
bool isNativeFP8 = AElType.isFloat8E5M2() || AElType.isFloat8E4M3FN();
347+
bool isNativeFP8 =
348+
llvm::isa<mlir::Float8E5M2Type, mlir::Float8E4M3FNType>(AElType);
348349
// promote operands for sm < 89 since fp8 mma is not natively supported
349350
// promote operands for sm >= 90 when mma is not v3
350351
if (!isNativeFP8 ||

‎lib/Dialect/TritonGPU/Transforms/Utility.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -44,9 +44,9 @@ SmallVector<unsigned, 3> mmaVersionToInstrShape(int version,
4444
SmallVector<unsigned> validN;
4545

4646
// MMAv3 with larger instruction shape is preferred.
47-
if (eltType.isFloat8E5M2() || eltType.isFloat8E4M3FN() ||
48-
eltType.isFloat8E4M3FNUZ() || eltType.isF16() || eltType.isBF16() ||
49-
eltType.isF32()) {
47+
if (llvm::isa<mlir::Float8E5M2Type, mlir::Float8E4M3FNType,
48+
mlir::Float8E4M3FNUZType>(eltType) ||
49+
eltType.isF16() || eltType.isBF16() || eltType.isF32()) {
5050
validN.assign({256, 248, 240, 232, 224, 216, 208, 200, 192, 184, 176,
5151
168, 160, 152, 144, 136, 128, 120, 112, 104, 96, 88,
5252
80, 72, 64, 56, 48, 40, 32, 24, 16, 8});

‎lib/Dialect/TritonNvidiaGPU/IR/Ops.cpp‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -77,8 +77,9 @@ bool WarpGroupDotOp::needsPartialAccumulator() {
7777
const auto &d = getD();
7878
auto aTensorTy = cast<triton::gpu::TensorOrMemDesc>(a.getType());
7979
auto aElTy = cast<triton::gpu::TensorOrMemDesc>(a.getType()).getElementType();
80-
bool isFP8 = aElTy.isFloat8E5M2() || aElTy.isFloat8E4M3FN() ||
81-
aElTy.isFloat8E5M2FNUZ() || aElTy.isFloat8E4M3FNUZ();
80+
bool isFP8 =
81+
llvm::isa<mlir::Float8E5M2Type, mlir::Float8E4M3FNType,
82+
mlir::Float8E5M2FNUZType, mlir::Float8E4M3FNUZType>(aElTy);
8283
bool accFP32 =
8384
cast<triton::gpu::TensorOrMemDesc>(d.getType()).getElementType().isF32();
8485
uint32_t maxNumImpreciseAcc = getMaxNumImpreciseAcc();

‎third_party/amd/lib/TritonAMDGPUToLLVM/ElementwiseOpToLLVM.cpp‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1019,17 +1019,17 @@ struct FpToFpOpConversion
10191019
return outVals;
10201020
}
10211021
size_t numElements = 4;
1022-
if (srcElementType.isFloat8E4M3FN() || dstElementType.isFloat8E4M3FN() ||
1023-
srcElementType.isFloat8E4M3FNUZ() ||
1024-
dstElementType.isFloat8E4M3FNUZ() ||
1025-
srcElementType.isFloat8E5M2FNUZ() ||
1026-
dstElementType.isFloat8E5M2FNUZ()) {
1022+
if (llvm::isa<mlir::Float8E4M3FNType, mlir::Float8E4M3FNUZType,
1023+
mlir::Float8E5M2FNUZType>(srcElementType) ||
1024+
llvm::isa<mlir::Float8E4M3FNType, mlir::Float8E4M3FNUZType,
1025+
mlir::Float8E5M2FNUZType>(dstElementType)) {
10271026
numElements = 2;
10281027
}
10291028
bool useFP16IntermediateSrc =
1030-
srcElementType.isF32() && !(isaFamily == AMD::ISAFamily::CDNA3 &&
1031-
(dstElementType.isFloat8E4M3FNUZ() ||
1032-
dstElementType.isFloat8E5M2FNUZ()));
1029+
srcElementType.isF32() &&
1030+
!(isaFamily == AMD::ISAFamily::CDNA3 &&
1031+
(llvm::isa<mlir::Float8E4M3FNUZType, mlir::Float8E5M2FNUZType>(
1032+
dstElementType)));
10331033
bool isDstFP32 = dstElementType.isF32();
10341034
Type srcType = useFP16IntermediateSrc ? f16_ty : srcElementType;
10351035
Type dstType = isDstFP32 ? f16_ty : dstElementType;

‎third_party/amd/lib/TritonAMDGPUTransforms/AccelerateAMDMatmul.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -416,7 +416,7 @@ class BlockedToMFMA : public OpRewritePattern<tt::DotOp> {
416416
// store instructions, except for fp8 matmul kernels due to regression
417417
// TODO (lixun): investigate the regression and enable this feature again
418418
auto aElemTy = mfmaInstr.getElementTypeA();
419-
bool isFP8 = aElemTy.isFloat8E5M2FNUZ() || aElemTy.isFloat8E4M3FNUZ();
419+
bool isFP8 = llvm::isa<Float8E5M2FNUZType, Float8E4M3FNUZType>(aElemTy);
420420
bool isTransposed = isChainDot(dotOp) || !isFP8;
421421
mfmaEnc = ttg::AMDMfmaEncodingAttr::get(
422422
oldRetType.getContext(),

‎third_party/amd/lib/TritonAMDGPUTransforms/MfmaGroup.cpp‎

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -20,19 +20,24 @@ static MfmaTypeId chooseAppropriateMfmaId(mlir::Type dataTypeA,
2020
if (dataTypeA.isInteger(8) && dataTypeB.isInteger(8)) {
2121
return MfmaTypeId::I8TyId;
2222
}
23-
if (dataTypeA.isFloat8E4M3FNUZ() && dataTypeB.isFloat8E4M3FNUZ()) {
23+
if (llvm::isa<mlir::Float8E4M3FNUZType>(dataTypeA) &&
24+
llvm::isa<mlir::Float8E4M3FNUZType>(dataTypeB)) {
2425
return MfmaTypeId::Fp8Fp8TyId;
2526
}
26-
if (dataTypeA.isFloat8E4M3FNUZ() && dataTypeB.isFloat8E5M2FNUZ()) {
27+
if (llvm::isa<mlir::Float8E4M3FNUZType>(dataTypeA) &&
28+
llvm::isa<mlir::Float8E5M2FNUZType>(dataTypeB)) {
2729
return MfmaTypeId::Fp8Bf8TyId;
2830
}
29-
if (dataTypeA.isFloat8E5M2FNUZ() && dataTypeB.isFloat8E4M3FNUZ()) {
31+
if (llvm::isa<mlir::Float8E5M2FNUZType>(dataTypeA) &&
32+
llvm::isa<mlir::Float8E4M3FNUZType>(dataTypeB)) {
3033
return MfmaTypeId::Bf8Fp8TyId;
3134
}
32-
if (dataTypeA.isFloat8E5M2FNUZ() && dataTypeB.isFloat8E5M2FNUZ()) {
35+
if (llvm::isa<mlir::Float8E5M2FNUZType>(dataTypeA) &&
36+
llvm::isa<mlir::Float8E5M2FNUZType>(dataTypeB)) {
3337
return MfmaTypeId::Bf8Bf8TyId;
3438
}
35-
if (dataTypeA.isFloat8E5M2() && dataTypeB.isFloat8E5M2()) {
39+
if (llvm::isa<mlir::Float8E5M2Type>(dataTypeA) &&
40+
llvm::isa<mlir::Float8E5M2Type>(dataTypeB)) {
3641
return MfmaTypeId::Fp16TyId;
3742
}
3843
llvm_unreachable("Unsupported input argument type.");

‎third_party/nvidia/lib/NVGPUToLLVM/NVGPUToLLVMPass.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
1010

1111
#include "nvidia/lib/TritonNVIDIAGPUToLLVM/Utility.h"
12+
#include "triton/Conversion/TritonGPUToLLVM/Utility.h"
1213
#include "llvm/Support/ErrorHandling.h"
1314

1415
using namespace mlir;

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