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[GR-68237] Fix GraalWasm SIMD performance issues found through vector-trunc-sat, vector-narrow and vector-q15mulr.
PullRequest: graal/21696
2 parents b0e0eea + 0026244 commit 2902e17

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-102
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13 files changed

+394
-102
lines changed

‎vm/mx.vm/mx_vm_gate.py‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -748,7 +748,11 @@ def gate_truffle_native_tck_wasm(tasks):
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mx.abort("Cannot resolve the `wasm:WASM` language distribution. To resolve this, import the wasm suite using `--dynamicimports /wasm`.")
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native_image_context, svm = graalvm_svm()
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with native_image_context(svm.IMAGE_ASSERTION_FLAGS) as native_image:
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_svm_truffle_tck(native_image, 'wasm', wasm_language)
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_svm_truffle_tck(native_image, 'wasm', wasm_language,
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# native-image sets -Djdk.internal.lambda.disableEagerInitialization=true by default,
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# which breaks Vector API's isNonCapturingLambda assertion. We override this property
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# for the GraalWasm Truffle Native TCK.
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additional_options=['-Djdk.internal.lambda.disableEagerInitialization=false'])
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def gate_maven_downloader(tasks):
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with Task('Maven Downloader prepare maven repo', tasks, tags=[VmGateTasks.maven_downloader]) as t:

‎wasm/scripts/run-wat-micro-benchmarks‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ VM=$2
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VM_CONFIG=$3
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UPLOAD_CMD=$4
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for benchmark in vector-double-mul vector-double-nearest vector-double-round vector-int-add vector-int-mix vector-int-mul
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for benchmark in vector-double-mul vector-double-nearest vector-double-round vector-int-add vector-int-mix vector-int-mul vector-narrow vector-q15mulr vector-trunc-sat
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do
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mx --dy /compiler --kill-with-sigquit benchmark \
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"--machine-name=${MACHINE_NAME}" \

‎wasm/src/org.graalvm.wasm.benchcases/src/bench/wat/vector-narrow.opts‎

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zero-memory = true
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interpreter-iterations = 1
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sync-noinline-iterations = 1
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sync-inline-iterations = 0
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async-iterations = 1050

‎wasm/src/org.graalvm.wasm.benchcases/src/bench/wat/vector-narrow.result‎

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1+
int 1

‎wasm/src/org.graalvm.wasm.benchcases/src/bench/wat/vector-narrow.wat‎

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;;
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;; Copyright (c) 2023, 2024, Oracle and/or its affiliates. All rights reserved.
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;; DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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;;
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;; The Universal Permissive License (UPL), Version 1.0
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;;
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;; Subject to the condition set forth below, permission is hereby granted to any
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;; person obtaining a copy of this software, associated documentation and/or
9+
;; data (collectively the "Software"), free of charge and under any and all
10+
;; copyright rights in the Software, and any and all patent rights owned or
11+
;; freely licensable by each licensor hereunder covering either (i) the
12+
;; unmodified Software as contributed to or provided by such licensor, or (ii)
13+
;; the Larger Works (as defined below), to deal in both
14+
;;
15+
;; (a) the Software, and
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;;
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;; (b) any piece of software and/or hardware listed in the lrgrwrks.txt file if
18+
;; one is included with the Software each a "Larger Work" to which the Software
19+
;; is contributed by such licensors),
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;;
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;; without restriction, including without limitation the rights to copy, create
22+
;; derivative works of, display, perform, and distribute the Software and make,
23+
;; use, sell, offer for sale, import, export, have made, and have sold the
24+
;; Software and the Larger Work(s), and to sublicense the foregoing rights on
25+
;; either these or other terms.
26+
;;
27+
;; This license is subject to the following condition:
28+
;;
29+
;; The above copyright notice and either this complete permission notice or at a
30+
;; minimum a reference to the UPL must be included in all copies or substantial
31+
;; portions of the Software.
32+
;;
33+
;; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
34+
;; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
35+
;; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
36+
;; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
37+
;; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
38+
;; OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
39+
;; SOFTWARE.
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;;
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(module
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(type $int_func (func (result i32)))
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(type $proc (func))
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(type $teardown_func (func (param i32)))
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(global $iterations i32 (i32.const 1000000))
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(memory $memory (export "memory") 0)
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(func (export "benchmarkSetupEach") (type $proc))
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(func (export "benchmarkTeardownEach") (type $teardown_func))
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(func (export "benchmarkRun") (type $int_func)
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(local $i i32)
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(local $acc v128)
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(local $x v128)
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(local $y v128)
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60+
(loop $bench_loop
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(local.set $x (i16x8.add (local.get $x) (v128.const i16x8 1 2 3 4 5 6 7 8)))
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(local.set $y (i16x8.add (local.get $y) (v128.const i16x8 9 10 11 12 13 14 15 16)))
63+
(local.set $acc (i8x16.add (local.get $acc) (i8x16.narrow_i16x8_s (local.get $x) (local.get $y))))
64+
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;; Increment loop counter and exit loop
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(local.set $i (i32.add (local.get $i) (i32.const 1)))
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(br_if $bench_loop (i32.lt_s (local.get $i) (global.get $iterations)))
68+
)
69+
70+
(v128.any_true (local.get $acc))
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)
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)

‎wasm/src/org.graalvm.wasm.benchcases/src/bench/wat/vector-q15mulr.opts‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
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zero-memory = true
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interpreter-iterations = 1
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sync-noinline-iterations = 1
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sync-inline-iterations = 0
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async-iterations = 1050

‎wasm/src/org.graalvm.wasm.benchcases/src/bench/wat/vector-q15mulr.result‎

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int 1

‎wasm/src/org.graalvm.wasm.benchcases/src/bench/wat/vector-q15mulr.wat‎

Lines changed: 69 additions & 0 deletions
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1+
;;
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;; Copyright (c) 2023, 2024, Oracle and/or its affiliates. All rights reserved.
3+
;; DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4+
;;
5+
;; The Universal Permissive License (UPL), Version 1.0
6+
;;
7+
;; Subject to the condition set forth below, permission is hereby granted to any
8+
;; person obtaining a copy of this software, associated documentation and/or
9+
;; data (collectively the "Software"), free of charge and under any and all
10+
;; copyright rights in the Software, and any and all patent rights owned or
11+
;; freely licensable by each licensor hereunder covering either (i) the
12+
;; unmodified Software as contributed to or provided by such licensor, or (ii)
13+
;; the Larger Works (as defined below), to deal in both
14+
;;
15+
;; (a) the Software, and
16+
;;
17+
;; (b) any piece of software and/or hardware listed in the lrgrwrks.txt file if
18+
;; one is included with the Software each a "Larger Work" to which the Software
19+
;; is contributed by such licensors),
20+
;;
21+
;; without restriction, including without limitation the rights to copy, create
22+
;; derivative works of, display, perform, and distribute the Software and make,
23+
;; use, sell, offer for sale, import, export, have made, and have sold the
24+
;; Software and the Larger Work(s), and to sublicense the foregoing rights on
25+
;; either these or other terms.
26+
;;
27+
;; This license is subject to the following condition:
28+
;;
29+
;; The above copyright notice and either this complete permission notice or at a
30+
;; minimum a reference to the UPL must be included in all copies or substantial
31+
;; portions of the Software.
32+
;;
33+
;; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
34+
;; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
35+
;; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
36+
;; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
37+
;; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
38+
;; OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
39+
;; SOFTWARE.
40+
;;
41+
(module
42+
(type $int_func (func (result i32)))
43+
(type $proc (func))
44+
(type $teardown_func (func (param i32)))
45+
46+
(global $iterations i32 (i32.const 1000000))
47+
48+
(memory $memory (export "memory") 0)
49+
50+
(func (export "benchmarkSetupEach") (type $proc))
51+
52+
(func (export "benchmarkTeardownEach") (type $teardown_func))
53+
54+
(func (export "benchmarkRun") (type $int_func)
55+
(local $i i32)
56+
(local $v v128)
57+
(local.set $v (v128.const i16x8 30000 31000 31500 20000 22500 12345 32145 123))
58+
59+
(loop $bench_loop
60+
(local.set $v (i16x8.q15mulr_sat_s (local.get $v) (v128.const i16x8 30000 3101 31499 34343 23123 4321 321 33333)))
61+
62+
;; Increment loop counter and exit loop
63+
(local.set $i (i32.add (local.get $i) (i32.const 1)))
64+
(br_if $bench_loop (i32.lt_s (local.get $i) (global.get $iterations)))
65+
)
66+
67+
(v128.any_true (local.get $v))
68+
)
69+
)

‎wasm/src/org.graalvm.wasm.benchcases/src/bench/wat/vector-trunc-sat.opts‎

Lines changed: 5 additions & 0 deletions
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@@ -0,0 +1,5 @@
1+
zero-memory = true
2+
interpreter-iterations = 1
3+
sync-noinline-iterations = 1
4+
sync-inline-iterations = 0
5+
async-iterations = 1050

‎wasm/src/org.graalvm.wasm.benchcases/src/bench/wat/vector-trunc-sat.result‎

Lines changed: 1 addition & 0 deletions
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int 1

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